/* SPDX-License-Identifier: GPL-2.0-only */ /* * UFS Host Controller driver for Exynos specific extensions * * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd. * */ #ifndef _UFS_EXYNOS_H_ #define _UFS_EXYNOS_H_ /* * Component registers */ #define COMP_CLK_PERIOD … /* * UNIPRO registers */ #define UNIPRO_DBG_FORCE_DME_CTRL_STATE … /* * MIBs for PA debug registers */ #define PA_DBG_CLK_PERIOD … #define PA_DBG_TXPHY_CFGUPDT … #define PA_DBG_RXPHY_CFGUPDT … #define PA_DBG_MODE … #define PA_DBG_SKIP_RESET_PHY … #define PA_DBG_AUTOMODE_THLD … #define PA_DBG_OV_TM … #define PA_DBG_SKIP_LINE_RESET … #define PA_DBG_LINE_RESET_REQ … #define PA_DBG_OPTION_SUITE … #define PA_DBG_OPTION_SUITE_DYN … /* * Note: GS101_DBG_OPTION offsets below differ from the TRM * but match the downstream driver. Following the TRM * results in non-functioning UFS. */ #define PA_GS101_DBG_OPTION_SUITE1 … #define PA_GS101_DBG_OPTION_SUITE2 … /* * MIBs for Transport Layer debug registers */ #define T_DBG_SKIP_INIT_HIBERN8_EXIT … /* * Exynos MPHY attributes */ #define TX_LINERESET_N_VAL … #define TX_LINERESET_N(v) … #define TX_LINERESET_P_VAL … #define TX_LINERESET_P(v) … #define TX_OV_SLEEP_CNT_TIMER … #define TX_OV_H8_ENTER_EN … #define TX_OV_SLEEP_CNT(v) … #define TX_HIGH_Z_CNT_11_08 … #define TX_HIGH_Z_CNT_H(v) … #define TX_HIGH_Z_CNT_07_00 … #define TX_HIGH_Z_CNT_L(v) … #define TX_BASE_NVAL_07_00 … #define TX_BASE_NVAL_L(v) … #define TX_BASE_NVAL_15_08 … #define TX_BASE_NVAL_H(v) … #define TX_GRAN_NVAL_07_00 … #define TX_GRAN_NVAL_L(v) … #define TX_GRAN_NVAL_10_08 … #define TX_GRAN_NVAL_H(v) … #define VND_TX_CLK_PRD … #define VND_TX_CLK_PRD_EN … #define VND_TX_LINERESET_PVALUE0 … #define VND_TX_LINERESET_PVALUE1 … #define VND_TX_LINERESET_PVALUE2 … #define TX_LINE_RESET_TIME … #define VND_RX_CLK_PRD … #define VND_RX_CLK_PRD_EN … #define VND_RX_LINERESET_VALUE0 … #define VND_RX_LINERESET_VALUE1 … #define VND_RX_LINERESET_VALUE2 … #define RX_LINE_RESET_TIME … #define RX_FILLER_ENABLE … #define RX_FILLER_EN … #define RX_LINERESET_VAL … #define RX_LINERESET(v) … #define RX_LCC_IGNORE … #define RX_SYNC_MASK_LENGTH … #define RX_HIBERN8_WAIT_VAL_BIT_20_16 … #define RX_HIBERN8_WAIT_VAL_BIT_15_08 … #define RX_HIBERN8_WAIT_VAL_BIT_07_00 … #define RX_OV_SLEEP_CNT_TIMER … #define RX_OV_SLEEP_CNT(v) … #define RX_OV_STALL_CNT_TIMER … #define RX_OV_STALL_CNT(v) … #define RX_BASE_NVAL_07_00 … #define RX_BASE_NVAL_L(v) … #define RX_BASE_NVAL_15_08 … #define RX_BASE_NVAL_H(v) … #define RX_GRAN_NVAL_07_00 … #define RX_GRAN_NVAL_L(v) … #define RX_GRAN_NVAL_10_08 … #define RX_GRAN_NVAL_H(v) … #define CMN_PWM_CLK_CTRL … #define PWM_CLK_CTRL_MASK … #define IATOVAL_NSEC … #define UNIPRO_PCLK_PERIOD(ufs) … struct exynos_ufs; /* vendor specific pre-defined parameters */ #define SLOW … #define FAST … #define RX_ADV_FINE_GRAN_SUP_EN … #define RX_ADV_FINE_GRAN_STEP_VAL … #define RX_ADV_MIN_ACTV_TIME_CAP … #define PA_GRANULARITY_VAL … #define PA_TACTIVATE_VAL … #define PA_HIBERN8TIME_VAL … #define PCLK_AVAIL_MIN … #define PCLK_AVAIL_MAX … struct exynos_ufs_uic_attr { … }; struct exynos_ufs_drv_data { … }; struct ufs_phy_time_cfg { … }; struct exynos_ufs { … }; #define for_each_ufs_rx_lane(ufs, i) … #define for_each_ufs_tx_lane(ufs, i) … #define EXYNOS_UFS_MMIO_FUNC … EXYNOS_UFS_MMIO_FUNC(hci); EXYNOS_UFS_MMIO_FUNC(unipro); EXYNOS_UFS_MMIO_FUNC(ufsp); #undef EXYNOS_UFS_MMIO_FUNC long exynos_ufs_calc_time_cntr(struct exynos_ufs *, long); static inline void exynos_ufs_enable_ov_tm(struct ufs_hba *hba) { … } static inline void exynos_ufs_disable_ov_tm(struct ufs_hba *hba) { … } static inline void exynos_ufs_enable_dbg_mode(struct ufs_hba *hba) { … } static inline void exynos_ufs_disable_dbg_mode(struct ufs_hba *hba) { … } #endif /* _UFS_EXYNOS_H_ */
Codebase Browser
linux