/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2010 - Maxim Levitsky * driver for Ricoh memstick readers */ #ifndef R592_H #include <linux/memstick.h> #include <linux/spinlock.h> #include <linux/interrupt.h> #include <linux/workqueue.h> #include <linux/kfifo.h> #include <linux/ctype.h> /* write to this reg (number,len) triggers TPC execution */ #define R592_TPC_EXEC … #define R592_TPC_EXEC_LEN_SHIFT … #define R592_TPC_EXEC_BIG_FIFO … #define R592_TPC_EXEC_TPC_SHIFT … /* Window for small TPC fifo (big endian)*/ /* reads and writes always are done in 8 byte chunks */ /* Not used in driver, because large fifo does better job */ #define R592_SFIFO … /* Status register (ms int, small fifo, IO)*/ #define R592_STATUS … /* Parallel INT bits */ #define R592_STATUS_P_CMDNACK … #define R592_STATUS_P_BREQ … #define R592_STATUS_P_INTERR … #define R592_STATUS_P_CED … /* Fifo status */ #define R592_STATUS_SFIFO_FULL … #define R592_STATUS_SFIFO_EMPTY … /* Error detection via CRC */ #define R592_STATUS_SEND_ERR … #define R592_STATUS_RECV_ERR … /* Card state */ #define R592_STATUS_RDY … #define R592_STATUS_CED … #define R592_STATUS_SFIFO_INPUT … #define R592_SFIFO_SIZE … #define R592_SFIFO_PACKET … /* IO control */ #define R592_IO … #define R592_IO_16 … #define R592_IO_18 … #define R592_IO_SERIAL1 … #define R592_IO_22 … #define R592_IO_DIRECTION … #define R592_IO_26 … #define R592_IO_SERIAL2 … #define R592_IO_RESET … /* Turns hardware on/off */ #define R592_POWER … #define R592_POWER_0 … #define R592_POWER_1 … #define R592_POWER_3 … #define R592_POWER_20 … /* IO mode*/ #define R592_IO_MODE … #define R592_IO_MODE_SERIAL … #define R592_IO_MODE_PARALLEL … /* IRQ,card detection,large fifo (first word irq status, second enable) */ /* IRQs are ACKed by clearing the bits */ #define R592_REG_MSC … #define R592_REG_MSC_PRSNT … #define R592_REG_MSC_IRQ_INSERT … #define R592_REG_MSC_IRQ_REMOVE … #define R592_REG_MSC_FIFO_EMPTY … #define R592_REG_MSC_FIFO_DMA_DONE … #define R592_REG_MSC_FIFO_USER_ORN … #define R592_REG_MSC_FIFO_MISMATH … #define R592_REG_MSC_FIFO_DMA_ERR … #define R592_REG_MSC_LED … #define DMA_IRQ_ACK_MASK … #define DMA_IRQ_EN_MASK … #define IRQ_ALL_ACK_MASK … #define IRQ_ALL_EN_MASK … /* DMA address for large FIFO read/writes*/ #define R592_FIFO_DMA … /* PIO access to large FIFO (512 bytes) (big endian)*/ #define R592_FIFO_PIO … #define R592_LFIFO_SIZE … /* large FIFO DMA settings */ #define R592_FIFO_DMA_SETTINGS … #define R592_FIFO_DMA_SETTINGS_EN … #define R592_FIFO_DMA_SETTINGS_DIR … #define R592_FIFO_DMA_SETTINGS_CAP … /* Maybe just an delay */ /* Bits 17..19 are just number */ /* bit 16 is set, then bit 20 is waited */ /* time to wait is about 50 spins * 2 ^ (bits 17..19) */ /* seems to be possible just to ignore */ /* Probably debug register */ #define R592_REG38 … #define R592_REG38_CHANGE … #define R592_REG38_DONE … #define R592_REG38_SHIFT … /* Debug register, written (0xABCDEF00) when error happens - not used*/ #define R592_REG_3C … struct r592_device { … }; #define DRV_NAME … #define message(format, ...) … #define __dbg(level, format, ...) … #define dbg(format, ...) … #define dbg_verbose(format, ...) … #define dbg_reg(format, ...) … #endif
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