/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MACH_IMX_CLK_H #define __MACH_IMX_CLK_H #include <linux/bits.h> #include <linux/spinlock.h> #include <linux/clk-provider.h> extern spinlock_t imx_ccm_lock; extern bool mcore_booted; void imx_check_clocks(struct clk *clks[], unsigned int count); void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); #ifndef MODULE void imx_register_uart_clocks(void); #else static inline void imx_register_uart_clocks(void) { } #endif void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn); void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count); extern void imx_cscmr1_fixup(u32 *val); enum imx_pllv1_type { … }; enum imx_sscg_pll_type { … }; enum imx_pll14xx_type { … }; enum imx_pllv4_type { … }; enum imx_pfdv2_type { … }; /* NOTE: Rate table should be kept sorted in descending order. */ struct imx_pll14xx_rate_table { … }; struct imx_pll14xx_clk { … }; extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; #define CLK_FRACN_GPPLL_INTEGER … #define CLK_FRACN_GPPLL_FRACN … /* NOTE: Rate table should be kept sorted in descending order. */ struct imx_fracn_gppll_rate_table { … }; struct imx_fracn_gppll_clk { … }; struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk); struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk); extern struct imx_fracn_gppll_clk imx_fracn_gppll; extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer; #define imx_clk_cpu(name, parent_name, div, mux, pll, step) … #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \ cgr_val, cgr_mask, clk_gate_flags, lock, share_count) … #define imx_clk_pllv3(type, name, parent_name, base, div_mask) … #define imx_clk_pfd(name, parent_name, reg, idx) … #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) … #define imx_clk_fixed(name, rate) … #define imx_clk_fixed_factor(name, parent, mult, div) … #define imx_clk_divider(name, parent, reg, shift, width) … #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) … #define imx_clk_gate(name, parent, reg, shift) … #define imx_clk_gate_dis(name, parent, reg, shift) … #define imx_clk_gate2(name, parent, reg, shift) … #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) … #define imx_clk_gate2_flags(name, parent, reg, shift, flags) … #define imx_clk_mux(name, reg, shift, width, parents, num_parents) … #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) … #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) … #define imx_clk_pllv1(type, name, parent, base) … #define imx_clk_pllv2(name, parent, base) … #define imx_clk_hw_gate(name, parent, reg, shift) … #define imx_clk_hw_gate2(name, parent, reg, shift) … #define imx_clk_hw_gate_dis(name, parent, reg, shift) … #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) … #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) … #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) … #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) … #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) … #define imx_clk_hw_gate3(name, parent, reg, shift) … #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) … #define imx_clk_hw_gate4(name, parent, reg, shift) … #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) … #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) … #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) … #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) … #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) … #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) … #define imx_clk_hw_divider(name, parent, reg, shift, width) … #define imx_clk_hw_divider2(name, parent, reg, shift, width) … #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) … #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) … struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name, const char *parent, void __iomem *base); struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, void __iomem *base); struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, void __iomem *base); struct clk_hw *imx_clk_hw_sscg_pll(const char *name, const char * const *parent_names, u8 num_parents, u8 parent, u8 bypass1, u8 bypass2, void __iomem *base, unsigned long flags); enum imx_pllv3_type { … }; struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask); #define PLL_1416X_RATE(_rate, _m, _p, _s) … #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) … struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name, const char *parent_name, void __iomem *base); struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask, u8 clk_gate_flags, spinlock_t *lock, unsigned int *share_count); struct clk * imx_obtain_fixed_clock( const char *name, unsigned long rate); struct clk_hw *imx_obtain_fixed_clock_hw( const char *name, unsigned long rate); struct clk_hw *imx_obtain_fixed_of_clock(struct device_node *np, const char *name, unsigned long rate); struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name); struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent, void __iomem *reg, u8 shift, u32 exclusive_mask); struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name, void __iomem *reg, u8 idx); struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name, const char *parent_name, void __iomem *reg, u8 idx); struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift); struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift, u8 width, void __iomem *busy_reg, u8 busy_shift, const char * const *parent_names, int num_parents); struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names, int num_parents, bool mux_present, bool rate_present, bool gate_present, void __iomem *reg); struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names, int num_parents, bool mux_present, bool rate_present, bool gate_present, void __iomem *reg, bool has_swrst); struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, void (*fixup)(u32 *val)); struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, void (*fixup)(u32 *val)); static inline struct clk *to_clk(struct clk_hw *hw) { … } static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate) { … } static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name, const char *parent, unsigned int mult, unsigned int div) { … } static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width) { … } static inline struct clk_hw *__imx_clk_hw_divider(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, unsigned long flags) { … } static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent, void __iomem *reg, u8 shift, unsigned long flags, unsigned long clk_gate_flags) { … } static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 cgr_val, unsigned long flags, unsigned int *share_count) { … } static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char * const *parents, int num_parents, unsigned long flags, unsigned long clk_mux_flags) { … } struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step); #define IMX_COMPOSITE_CORE … #define IMX_COMPOSITE_BUS … #define IMX_COMPOSITE_FW_MANAGED … #define IMX_COMPOSITE_CLK_FLAGS_DEFAULT … #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL … #define IMX_COMPOSITE_CLK_FLAGS_GET_RATE_NO_CACHE … #define IMX_COMPOSITE_CLK_FLAGS_CRITICAL_GET_RATE_NO_CACHE … struct clk_hw *__imx8m_clk_hw_composite(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, u32 composite_flags, unsigned long flags); #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) … #define imx8m_clk_hw_composite(name, parent_names, reg) … #define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) … #define imx8m_clk_hw_composite_critical(name, parent_names, reg) … #define imx8m_clk_hw_composite_bus(name, parent_names, reg) … #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) … #define imx8m_clk_hw_composite_core(name, parent_names, reg) … #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) … #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) … struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, u32 domain_id, unsigned long flags); #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) … struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val, u32 mask, u32 domain_id, unsigned int *share_count); struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock); struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible, u32 reg, const char **parent_names, u8 num_parents, const u32 *mux_table, u32 mask); #endif
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