linux/drivers/clk/imx/clk-composite-93.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2021 NXP
 *
 * Peng Fan <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>

#include "clk.h"

#define TIMEOUT_US …

#define CCM_DIV_SHIFT …
#define CCM_DIV_WIDTH …
#define CCM_MUX_SHIFT …
#define CCM_MUX_MASK …
#define CCM_OFF_SHIFT …
#define CCM_BUSY_SHIFT …

#define STAT_OFFSET …
#define AUTHEN_OFFSET …
#define TZ_NS_SHIFT …
#define TZ_NS_MASK …

#define WHITE_LIST_SHIFT …

static int imx93_clk_composite_wait_ready(struct clk_hw *hw, void __iomem *reg)
{ … }

static void imx93_clk_composite_gate_endisable(struct clk_hw *hw, int enable)
{ … }

static int imx93_clk_composite_gate_enable(struct clk_hw *hw)
{ … }

static void imx93_clk_composite_gate_disable(struct clk_hw *hw)
{ … }

static const struct clk_ops imx93_clk_composite_gate_ops = …;

static unsigned long
imx93_clk_composite_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ … }

static long
imx93_clk_composite_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
{ … }

static int
imx93_clk_composite_divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{ … }

static int imx93_clk_composite_divider_set_rate(struct clk_hw *hw, unsigned long rate,
						unsigned long parent_rate)
{ … }

static const struct clk_ops imx93_clk_composite_divider_ops = …;

static u8 imx93_clk_composite_mux_get_parent(struct clk_hw *hw)
{ … }

static int imx93_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
{ … }

static int
imx93_clk_composite_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{ … }

static const struct clk_ops imx93_clk_composite_mux_ops = …;

struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names,
					 int num_parents, void __iomem *reg, u32 domain_id,
					 unsigned long flags)
{ … }
EXPORT_SYMBOL_GPL(…);