// SPDX-License-Identifier: GPL-2.0 /* * Copyright 2021 NXP */ #include <linux/bitfield.h> #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/export.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/slab.h> #include <asm/div64.h> #include "clk.h" #define PLL_CTRL … #define HW_CTRL_SEL … #define CLKMUX_BYPASS … #define CLKMUX_EN … #define POWERUP_MASK … #define PLL_ANA_PRG … #define PLL_SPREAD_SPECTRUM … #define PLL_NUMERATOR … #define PLL_MFN_MASK … #define PLL_DENOMINATOR … #define PLL_MFD_MASK … #define PLL_DIV … #define PLL_MFI_MASK … #define PLL_RDIV_MASK … #define PLL_ODIV_MASK … #define PLL_DFS_CTRL(x) … #define PLL_STATUS … #define LOCK_STATUS … #define DFS_STATUS … #define LOCK_TIMEOUT_US … #define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv) … #define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv) … struct clk_fracn_gppll { … }; /* * Fvco = (Fref / rdiv) * (MFI + MFN / MFD) * Fout = Fvco / odiv * The (Fref / rdiv) should be in range 20MHz to 40MHz * The Fvco should be in range 2.5Ghz to 5Ghz */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = …; struct imx_fracn_gppll_clk imx_fracn_gppll = …; EXPORT_SYMBOL_GPL(…); /* * Fvco = (Fref / rdiv) * MFI * Fout = Fvco / odiv * The (Fref / rdiv) should be in range 20MHz to 40MHz * The Fvco should be in range 2.5Ghz to 5Ghz */ static const struct imx_fracn_gppll_rate_table int_tbl[] = …; struct imx_fracn_gppll_clk imx_fracn_gppll_integer = …; EXPORT_SYMBOL_GPL(…); static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw) { … } static const struct imx_fracn_gppll_rate_table * imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate) { … } static long clk_fracn_gppll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll) { … } static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, unsigned long prate) { … } static int clk_fracn_gppll_prepare(struct clk_hw *hw) { … } static int clk_fracn_gppll_is_prepared(struct clk_hw *hw) { … } static void clk_fracn_gppll_unprepare(struct clk_hw *hw) { … } static const struct clk_ops clk_fracn_gppll_ops = …; static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk, u32 pll_flags) { … } struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk) { … } EXPORT_SYMBOL_GPL(…); struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk) { … } EXPORT_SYMBOL_GPL(…);
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