linux/drivers/clk/imx/clk-composite-7ulp.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017~2018 NXP
 *
 */

#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>

#include "../clk-fractional-divider.h"
#include "clk.h"

#define PCG_PCS_SHIFT …
#define PCG_PCS_MASK …
#define PCG_CGC_SHIFT …
#define PCG_FRAC_SHIFT …
#define PCG_FRAC_WIDTH …
#define PCG_PCD_SHIFT …
#define PCG_PCD_WIDTH …

#define SW_RST …

static int pcc_gate_enable(struct clk_hw *hw)
{ … }

static void pcc_gate_disable(struct clk_hw *hw)
{ … }

static int pcc_gate_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops pcc_gate_ops = …;

static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
				     const char * const *parent_names,
				     int num_parents, bool mux_present,
				     bool rate_present, bool gate_present,
				     void __iomem *reg, bool has_swrst)
{ … }

struct clk_hw *imx7ulp_clk_hw_composite(const char *name, const char * const *parent_names,
				int num_parents, bool mux_present, bool rate_present,
				bool gate_present, void __iomem *reg)
{ … }

struct clk_hw *imx8ulp_clk_hw_composite(const char *name, const char * const *parent_names,
				int num_parents, bool mux_present, bool rate_present,
				bool gate_present, void __iomem *reg, bool has_swrst)
{ … }
EXPORT_SYMBOL_GPL(…);