// SPDX-License-Identifier: GPL-2.0 /* * Copyright 2018 NXP. * * This driver supports the fractional plls found in the imx8m SOCs * * Documentation for this fractional pll can be found at: * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834 */ #include <linux/clk-provider.h> #include <linux/err.h> #include <linux/export.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/slab.h> #include <linux/bitfield.h> #include "clk.h" #define PLL_CFG0 … #define PLL_CFG1 … #define PLL_LOCK_STATUS … #define PLL_PD_MASK … #define PLL_BYPASS_MASK … #define PLL_NEWDIV_VAL … #define PLL_NEWDIV_ACK … #define PLL_FRAC_DIV_MASK … #define PLL_INT_DIV_MASK … #define PLL_OUTPUT_DIV_MASK … #define PLL_FRAC_DENOM … #define PLL_FRAC_LOCK_TIMEOUT … #define PLL_FRAC_ACK_TIMEOUT … struct clk_frac_pll { … }; #define to_clk_frac_pll(_hw) … static int clk_wait_lock(struct clk_frac_pll *pll) { … } static int clk_wait_ack(struct clk_frac_pll *pll) { … } static int clk_pll_prepare(struct clk_hw *hw) { … } static void clk_pll_unprepare(struct clk_hw *hw) { … } static int clk_pll_is_prepared(struct clk_hw *hw) { … } static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } /* * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero * (means the PLL output will be divided by 2). So the PLL output can use * the below formula: * pllout = parent_rate * 8 / 2 * DIVF_VAL; * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24. */ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops clk_frac_pll_ops = …; struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name, void __iomem *base) { … } EXPORT_SYMBOL_GPL(…);
Codebase Browser
linux