linux/drivers/clk/imx/clk-gate2.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2010-2011 Canonical Ltd <[email protected]>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <[email protected]>
 *
 * Gated clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/export.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include "clk.h"

/**
 * DOC: basic gateable clock which can gate and ungate its output
 *
 * Traits of this clock:
 * prepare - clk_(un)prepare only ensures parent is (un)prepared
 * enable - clk_enable and clk_disable are functional & control gating
 * rate - inherits rate from parent.  No clk_set_rate support
 * parent - fixed parent.  No clk_set_parent support
 */

struct clk_gate2 { … };

#define to_clk_gate2(_hw) …

static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable)
{ … }

static int clk_gate2_enable(struct clk_hw *hw)
{ … }

static void clk_gate2_disable(struct clk_hw *hw)
{ … }

static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx,
					u8 cgr_val, u8 cgr_mask)
{ … }

static int clk_gate2_is_enabled(struct clk_hw *hw)
{ … }

static void clk_gate2_disable_unused(struct clk_hw *hw)
{ … }

static const struct clk_ops clk_gate2_ops = …;

struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
		const char *parent_name, unsigned long flags,
		void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
		u8 clk_gate2_flags, spinlock_t *lock,
		unsigned int *share_count)
{ … }
EXPORT_SYMBOL_GPL(…);