// SPDX-License-Identifier: GPL-2.0 #include <linux/kernel.h> #include <linux/clk.h> #include <linux/io.h> #include <linux/errno.h> #include <linux/delay.h> #include <linux/slab.h> #include <linux/err.h> #include <asm/div64.h> #include "clk.h" #define to_clk_pllv2(clk) … /* PLL Register Offsets */ #define MXC_PLL_DP_CTL … #define MXC_PLL_DP_CONFIG … #define MXC_PLL_DP_OP … #define MXC_PLL_DP_MFD … #define MXC_PLL_DP_MFN … #define MXC_PLL_DP_MFNMINUS … #define MXC_PLL_DP_MFNPLUS … #define MXC_PLL_DP_HFS_OP … #define MXC_PLL_DP_HFS_MFD … #define MXC_PLL_DP_HFS_MFN … #define MXC_PLL_DP_MFN_TOGC … #define MXC_PLL_DP_DESTAT … /* PLL Register Bit definitions */ #define MXC_PLL_DP_CTL_MUL_CTRL … #define MXC_PLL_DP_CTL_DPDCK0_2_EN … #define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET … #define MXC_PLL_DP_CTL_ADE … #define MXC_PLL_DP_CTL_REF_CLK_DIV … #define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK … #define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET … #define MXC_PLL_DP_CTL_HFSM … #define MXC_PLL_DP_CTL_PRE … #define MXC_PLL_DP_CTL_UPEN … #define MXC_PLL_DP_CTL_RST … #define MXC_PLL_DP_CTL_RCP … #define MXC_PLL_DP_CTL_PLM … #define MXC_PLL_DP_CTL_BRM0 … #define MXC_PLL_DP_CTL_LRF … #define MXC_PLL_DP_CONFIG_BIST … #define MXC_PLL_DP_CONFIG_SJC_CE … #define MXC_PLL_DP_CONFIG_AREN … #define MXC_PLL_DP_CONFIG_LDREQ … #define MXC_PLL_DP_OP_MFI_OFFSET … #define MXC_PLL_DP_OP_MFI_MASK … #define MXC_PLL_DP_OP_PDF_OFFSET … #define MXC_PLL_DP_OP_PDF_MASK … #define MXC_PLL_DP_MFD_OFFSET … #define MXC_PLL_DP_MFD_MASK … #define MXC_PLL_DP_MFN_OFFSET … #define MXC_PLL_DP_MFN_MASK … #define MXC_PLL_DP_MFN_TOGC_TOG_DIS … #define MXC_PLL_DP_MFN_TOGC_TOG_EN … #define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET … #define MXC_PLL_DP_MFN_TOGC_CNT_MASK … #define MXC_PLL_DP_DESTAT_TOG_SEL … #define MXC_PLL_DP_DESTAT_MFN … #define MAX_DPLL_WAIT_TRIES … struct clk_pllv2 { … }; static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate, u32 dp_ctl, u32 dp_op, u32 dp_mfd, u32 dp_mfn) { … } static unsigned long clk_pllv2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate, u32 *dp_op, u32 *dp_mfd, u32 *dp_mfn) { … } static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int clk_pllv2_prepare(struct clk_hw *hw) { … } static void clk_pllv2_unprepare(struct clk_hw *hw) { … } static const struct clk_ops clk_pllv2_ops = …; struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent, void __iomem *base) { … }
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