linux/drivers/clk/imx/clk-pllv3.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 * Copyright 2012 Linaro Ltd.
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include "clk.h"

#define PLL_NUM_OFFSET …
#define PLL_DENOM_OFFSET …
#define PLL_IMX7_NUM_OFFSET …
#define PLL_IMX7_DENOM_OFFSET …

#define PLL_VF610_NUM_OFFSET …
#define PLL_VF610_DENOM_OFFSET …

#define BM_PLL_POWER …
#define BM_PLL_LOCK …
#define IMX7_ENET_PLL_POWER …
#define IMX7_DDR_PLL_POWER …

#define PLL_LOCK_TIMEOUT …

/**
 * struct clk_pllv3 - IMX PLL clock version 3
 * @hw:		clock source
 * @base:	 base address of PLL registers
 * @power_bit:	 pll power bit mask
 * @powerup_set: set power_bit to power up the PLL
 * @div_mask:	 mask of divider bits
 * @div_shift:	 shift of divider bits
 * @ref_clock:	reference clock rate
 * @num_offset:	num register offset
 * @denom_offset: denom register offset
 *
 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
 * is actually a multiplier, and always sits at bit 0.
 */
struct clk_pllv3 { … };

#define to_clk_pllv3(_hw) …

static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
{ … }

static int clk_pllv3_prepare(struct clk_hw *hw)
{ … }

static void clk_pllv3_unprepare(struct clk_hw *hw)
{ … }

static int clk_pllv3_is_prepared(struct clk_hw *hw)
{ … }

static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{ … }

static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *prate)
{ … }

static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static const struct clk_ops clk_pllv3_ops = …;

static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
					       unsigned long parent_rate)
{ … }

static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
				     unsigned long *prate)
{ … }

static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static const struct clk_ops clk_pllv3_sys_ops = …;

static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{ … }

static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{ … }

static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static const struct clk_ops clk_pllv3_av_ops = …;

struct clk_pllv3_vf610_mf { … };

static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
		struct clk_pllv3_vf610_mf mf)
{ … }

static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
		unsigned long parent_rate, unsigned long rate)
{ … }

static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
					      unsigned long parent_rate)
{ … }

static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
				    unsigned long *prate)
{ … }

static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
{ … }

static const struct clk_ops clk_pllv3_vf610_ops = …;

static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{ … }

static const struct clk_ops clk_pllv3_enet_ops = …;

struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
			  const char *parent_name, void __iomem *base,
			  u32 div_mask)
{ … }
EXPORT_SYMBOL_GPL(…);