linux/drivers/clk/imx/clk-pllv4.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017~2018 NXP
 *
 * Author: Dong Aisheng <[email protected]>
 *
 */

#include <linux/bits.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>

#include "clk.h"

/* PLL Control Status Register (xPLLCSR) */
#define PLL_CSR_OFFSET …
#define PLL_VLD …
#define PLL_EN …

/* PLL Configuration Register (xPLLCFG) */
#define PLL_CFG_OFFSET …
#define IMX8ULP_PLL_CFG_OFFSET …
#define BP_PLL_MULT …
#define BM_PLL_MULT …

/* PLL Numerator Register (xPLLNUM) */
#define PLL_NUM_OFFSET …
#define IMX8ULP_PLL_NUM_OFFSET …

/* PLL Denominator Register (xPLLDENOM) */
#define PLL_DENOM_OFFSET …
#define IMX8ULP_PLL_DENOM_OFFSET …

#define MAX_MFD …
#define DEFAULT_MFD …

struct clk_pllv4 { … };

/* Valid PLL MULT Table */
static const int pllv4_mult_table[] = …;

/* Valid PLL MULT range, (max, min) */
static const int pllv4_mult_range[] = …;

#define to_clk_pllv4(__hw) …

#define LOCK_TIMEOUT_US …

static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
{ … }

static int clk_pllv4_is_prepared(struct clk_hw *hw)
{ … }

static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{ … }

static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
				 unsigned long *prate)
{ … }

static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
{ … }

static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long parent_rate)
{ … }

static int clk_pllv4_prepare(struct clk_hw *hw)
{ … }

static void clk_pllv4_unprepare(struct clk_hw *hw)
{ … }

static const struct clk_ops clk_pllv4_ops = …;

struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
		 const char *parent_name, void __iomem *base)
{ … }
EXPORT_SYMBOL_GPL(…);