/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2018-2019 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8MN_H #define __DT_BINDINGS_CLOCK_IMX8MN_H #define IMX8MN_CLK_DUMMY … #define IMX8MN_CLK_32K … #define IMX8MN_CLK_24M … #define IMX8MN_OSC_HDMI_CLK … #define IMX8MN_CLK_EXT1 … #define IMX8MN_CLK_EXT2 … #define IMX8MN_CLK_EXT3 … #define IMX8MN_CLK_EXT4 … #define IMX8MN_AUDIO_PLL1_REF_SEL … #define IMX8MN_AUDIO_PLL2_REF_SEL … #define IMX8MN_VIDEO_PLL_REF_SEL … #define IMX8MN_VIDEO_PLL1_REF_SEL … #define IMX8MN_DRAM_PLL_REF_SEL … #define IMX8MN_GPU_PLL_REF_SEL … #define IMX8MN_M7_ALT_PLL_REF_SEL … #define IMX8MN_VPU_PLL_REF_SEL … #define IMX8MN_ARM_PLL_REF_SEL … #define IMX8MN_SYS_PLL1_REF_SEL … #define IMX8MN_SYS_PLL2_REF_SEL … #define IMX8MN_SYS_PLL3_REF_SEL … #define IMX8MN_AUDIO_PLL1 … #define IMX8MN_AUDIO_PLL2 … #define IMX8MN_VIDEO_PLL … #define IMX8MN_VIDEO_PLL1 … #define IMX8MN_DRAM_PLL … #define IMX8MN_GPU_PLL … #define IMX8MN_M7_ALT_PLL … #define IMX8MN_VPU_PLL … #define IMX8MN_ARM_PLL … #define IMX8MN_SYS_PLL1 … #define IMX8MN_SYS_PLL2 … #define IMX8MN_SYS_PLL3 … #define IMX8MN_AUDIO_PLL1_BYPASS … #define IMX8MN_AUDIO_PLL2_BYPASS … #define IMX8MN_VIDEO_PLL_BYPASS … #define IMX8MN_VIDEO_PLL1_BYPASS … #define IMX8MN_DRAM_PLL_BYPASS … #define IMX8MN_GPU_PLL_BYPASS … #define IMX8MN_M7_ALT_PLL_BYPASS … #define IMX8MN_VPU_PLL_BYPASS … #define IMX8MN_ARM_PLL_BYPASS … #define IMX8MN_SYS_PLL1_BYPASS … #define IMX8MN_SYS_PLL2_BYPASS … #define IMX8MN_SYS_PLL3_BYPASS … #define IMX8MN_AUDIO_PLL1_OUT … #define IMX8MN_AUDIO_PLL2_OUT … #define IMX8MN_VIDEO_PLL_OUT … #define IMX8MN_VIDEO_PLL1_OUT … #define IMX8MN_DRAM_PLL_OUT … #define IMX8MN_GPU_PLL_OUT … #define IMX8MN_M7_ALT_PLL_OUT … #define IMX8MN_VPU_PLL_OUT … #define IMX8MN_ARM_PLL_OUT … #define IMX8MN_SYS_PLL1_OUT … #define IMX8MN_SYS_PLL2_OUT … #define IMX8MN_SYS_PLL3_OUT … #define IMX8MN_SYS_PLL1_40M … #define IMX8MN_SYS_PLL1_80M … #define IMX8MN_SYS_PLL1_100M … #define IMX8MN_SYS_PLL1_133M … #define IMX8MN_SYS_PLL1_160M … #define IMX8MN_SYS_PLL1_200M … #define IMX8MN_SYS_PLL1_266M … #define IMX8MN_SYS_PLL1_400M … #define IMX8MN_SYS_PLL1_800M … #define IMX8MN_SYS_PLL2_50M … #define IMX8MN_SYS_PLL2_100M … #define IMX8MN_SYS_PLL2_125M … #define IMX8MN_SYS_PLL2_166M … #define IMX8MN_SYS_PLL2_200M … #define IMX8MN_SYS_PLL2_250M … #define IMX8MN_SYS_PLL2_333M … #define IMX8MN_SYS_PLL2_500M … #define IMX8MN_SYS_PLL2_1000M … /* CORE CLOCK ROOT */ #define IMX8MN_CLK_A53_SRC … #define IMX8MN_CLK_GPU_CORE_SRC … #define IMX8MN_CLK_GPU_SHADER_SRC … #define IMX8MN_CLK_A53_CG … #define IMX8MN_CLK_GPU_CORE_CG … #define IMX8MN_CLK_GPU_SHADER_CG … #define IMX8MN_CLK_A53_DIV … #define IMX8MN_CLK_GPU_CORE_DIV … #define IMX8MN_CLK_GPU_SHADER_DIV … /* BUS CLOCK ROOT */ #define IMX8MN_CLK_MAIN_AXI … #define IMX8MN_CLK_ENET_AXI … #define IMX8MN_CLK_NAND_USDHC_BUS … #define IMX8MN_CLK_DISP_AXI … #define IMX8MN_CLK_DISP_APB … #define IMX8MN_CLK_USB_BUS … #define IMX8MN_CLK_GPU_AXI … #define IMX8MN_CLK_GPU_AHB … #define IMX8MN_CLK_NOC … #define IMX8MN_CLK_AHB … #define IMX8MN_CLK_AUDIO_AHB … /* IPG CLOCK ROOT */ #define IMX8MN_CLK_IPG_ROOT … #define IMX8MN_CLK_IPG_AUDIO_ROOT … /* IP */ #define IMX8MN_CLK_DRAM_CORE … #define IMX8MN_CLK_DRAM_ALT … #define IMX8MN_CLK_DRAM_APB … #define IMX8MN_CLK_DRAM_ALT_ROOT … #define IMX8MN_CLK_DISP_PIXEL … #define IMX8MN_CLK_SAI2 … #define IMX8MN_CLK_SAI3 … #define IMX8MN_CLK_SAI5 … #define IMX8MN_CLK_SAI6 … #define IMX8MN_CLK_SPDIF1 … #define IMX8MN_CLK_ENET_REF … #define IMX8MN_CLK_ENET_TIMER … #define IMX8MN_CLK_ENET_PHY_REF … #define IMX8MN_CLK_NAND … #define IMX8MN_CLK_QSPI … #define IMX8MN_CLK_USDHC1 … #define IMX8MN_CLK_USDHC2 … #define IMX8MN_CLK_I2C1 … #define IMX8MN_CLK_I2C2 … #define IMX8MN_CLK_I2C3 … #define IMX8MN_CLK_I2C4 … #define IMX8MN_CLK_UART1 … #define IMX8MN_CLK_UART2 … #define IMX8MN_CLK_UART3 … #define IMX8MN_CLK_UART4 … #define IMX8MN_CLK_USB_CORE_REF … #define IMX8MN_CLK_USB_PHY_REF … #define IMX8MN_CLK_ECSPI1 … #define IMX8MN_CLK_ECSPI2 … #define IMX8MN_CLK_PWM1 … #define IMX8MN_CLK_PWM2 … #define IMX8MN_CLK_PWM3 … #define IMX8MN_CLK_PWM4 … #define IMX8MN_CLK_WDOG … #define IMX8MN_CLK_WRCLK … #define IMX8MN_CLK_CLKO1 … #define IMX8MN_CLK_CLKO2 … #define IMX8MN_CLK_DSI_CORE … #define IMX8MN_CLK_DSI_PHY_REF … #define IMX8MN_CLK_DSI_DBI … #define IMX8MN_CLK_USDHC3 … #define IMX8MN_CLK_CAMERA_PIXEL … #define IMX8MN_CLK_CSI1_PHY_REF … #define IMX8MN_CLK_CSI2_PHY_REF … #define IMX8MN_CLK_CSI2_ESC … #define IMX8MN_CLK_ECSPI3 … #define IMX8MN_CLK_PDM … #define IMX8MN_CLK_SAI7 … #define IMX8MN_CLK_ECSPI1_ROOT … #define IMX8MN_CLK_ECSPI2_ROOT … #define IMX8MN_CLK_ECSPI3_ROOT … #define IMX8MN_CLK_ENET1_ROOT … #define IMX8MN_CLK_GPIO1_ROOT … #define IMX8MN_CLK_GPIO2_ROOT … #define IMX8MN_CLK_GPIO3_ROOT … #define IMX8MN_CLK_GPIO4_ROOT … #define IMX8MN_CLK_GPIO5_ROOT … #define IMX8MN_CLK_I2C1_ROOT … #define IMX8MN_CLK_I2C2_ROOT … #define IMX8MN_CLK_I2C3_ROOT … #define IMX8MN_CLK_I2C4_ROOT … #define IMX8MN_CLK_MU_ROOT … #define IMX8MN_CLK_OCOTP_ROOT … #define IMX8MN_CLK_PWM1_ROOT … #define IMX8MN_CLK_PWM2_ROOT … #define IMX8MN_CLK_PWM3_ROOT … #define IMX8MN_CLK_PWM4_ROOT … #define IMX8MN_CLK_QSPI_ROOT … #define IMX8MN_CLK_NAND_ROOT … #define IMX8MN_CLK_SAI2_ROOT … #define IMX8MN_CLK_SAI2_IPG … #define IMX8MN_CLK_SAI3_ROOT … #define IMX8MN_CLK_SAI3_IPG … #define IMX8MN_CLK_SAI5_ROOT … #define IMX8MN_CLK_SAI5_IPG … #define IMX8MN_CLK_SAI6_ROOT … #define IMX8MN_CLK_SAI6_IPG … #define IMX8MN_CLK_SAI7_ROOT … #define IMX8MN_CLK_SAI7_IPG … #define IMX8MN_CLK_SDMA1_ROOT … #define IMX8MN_CLK_SDMA2_ROOT … #define IMX8MN_CLK_UART1_ROOT … #define IMX8MN_CLK_UART2_ROOT … #define IMX8MN_CLK_UART3_ROOT … #define IMX8MN_CLK_UART4_ROOT … #define IMX8MN_CLK_USB1_CTRL_ROOT … #define IMX8MN_CLK_USDHC1_ROOT … #define IMX8MN_CLK_USDHC2_ROOT … #define IMX8MN_CLK_WDOG1_ROOT … #define IMX8MN_CLK_WDOG2_ROOT … #define IMX8MN_CLK_WDOG3_ROOT … #define IMX8MN_CLK_GPU_BUS_ROOT … #define IMX8MN_CLK_ASRC_ROOT … #define IMX8MN_CLK_GPU3D_ROOT … #define IMX8MN_CLK_PDM_ROOT … #define IMX8MN_CLK_PDM_IPG … #define IMX8MN_CLK_DISP_AXI_ROOT … #define IMX8MN_CLK_DISP_APB_ROOT … #define IMX8MN_CLK_DISP_PIXEL_ROOT … #define IMX8MN_CLK_CAMERA_PIXEL_ROOT … #define IMX8MN_CLK_USDHC3_ROOT … #define IMX8MN_CLK_SDMA3_ROOT … #define IMX8MN_CLK_TMU_ROOT … #define IMX8MN_CLK_ARM … #define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK … #define IMX8MN_CLK_GPU_CORE_ROOT … #define IMX8MN_CLK_GIC … #define IMX8MN_SYS_PLL1_40M_CG … #define IMX8MN_SYS_PLL1_80M_CG … #define IMX8MN_SYS_PLL1_100M_CG … #define IMX8MN_SYS_PLL1_133M_CG … #define IMX8MN_SYS_PLL1_160M_CG … #define IMX8MN_SYS_PLL1_200M_CG … #define IMX8MN_SYS_PLL1_266M_CG … #define IMX8MN_SYS_PLL1_400M_CG … #define IMX8MN_SYS_PLL2_50M_CG … #define IMX8MN_SYS_PLL2_100M_CG … #define IMX8MN_SYS_PLL2_125M_CG … #define IMX8MN_SYS_PLL2_166M_CG … #define IMX8MN_SYS_PLL2_200M_CG … #define IMX8MN_SYS_PLL2_250M_CG … #define IMX8MN_SYS_PLL2_333M_CG … #define IMX8MN_SYS_PLL2_500M_CG … #define IMX8MN_CLK_SNVS_ROOT … #define IMX8MN_CLK_GPU_CORE … #define IMX8MN_CLK_GPU_SHADER … #define IMX8MN_CLK_A53_CORE … #define IMX8MN_CLK_CLKOUT1_SEL … #define IMX8MN_CLK_CLKOUT1_DIV … #define IMX8MN_CLK_CLKOUT1 … #define IMX8MN_CLK_CLKOUT2_SEL … #define IMX8MN_CLK_CLKOUT2_DIV … #define IMX8MN_CLK_CLKOUT2 … #define IMX8MN_CLK_M7_CORE … #define IMX8MN_CLK_GPT_3M … #define IMX8MN_CLK_GPT1 … #define IMX8MN_CLK_GPT1_ROOT … #define IMX8MN_CLK_GPT2 … #define IMX8MN_CLK_GPT2_ROOT … #define IMX8MN_CLK_GPT3 … #define IMX8MN_CLK_GPT3_ROOT … #define IMX8MN_CLK_GPT4 … #define IMX8MN_CLK_GPT4_ROOT … #define IMX8MN_CLK_GPT5 … #define IMX8MN_CLK_GPT5_ROOT … #define IMX8MN_CLK_GPT6 … #define IMX8MN_CLK_GPT6_ROOT … #define IMX8MN_CLK_END … #endif
Codebase Browser
linux