/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright 2017-2018 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8MM_H #define __DT_BINDINGS_CLOCK_IMX8MM_H #define IMX8MM_CLK_DUMMY … #define IMX8MM_CLK_32K … #define IMX8MM_CLK_24M … #define IMX8MM_OSC_HDMI_CLK … #define IMX8MM_CLK_EXT1 … #define IMX8MM_CLK_EXT2 … #define IMX8MM_CLK_EXT3 … #define IMX8MM_CLK_EXT4 … #define IMX8MM_AUDIO_PLL1_REF_SEL … #define IMX8MM_AUDIO_PLL2_REF_SEL … #define IMX8MM_VIDEO_PLL1_REF_SEL … #define IMX8MM_DRAM_PLL_REF_SEL … #define IMX8MM_GPU_PLL_REF_SEL … #define IMX8MM_VPU_PLL_REF_SEL … #define IMX8MM_ARM_PLL_REF_SEL … #define IMX8MM_SYS_PLL1_REF_SEL … #define IMX8MM_SYS_PLL2_REF_SEL … #define IMX8MM_SYS_PLL3_REF_SEL … #define IMX8MM_AUDIO_PLL1 … #define IMX8MM_AUDIO_PLL2 … #define IMX8MM_VIDEO_PLL1 … #define IMX8MM_DRAM_PLL … #define IMX8MM_GPU_PLL … #define IMX8MM_VPU_PLL … #define IMX8MM_ARM_PLL … #define IMX8MM_SYS_PLL1 … #define IMX8MM_SYS_PLL2 … #define IMX8MM_SYS_PLL3 … #define IMX8MM_AUDIO_PLL1_BYPASS … #define IMX8MM_AUDIO_PLL2_BYPASS … #define IMX8MM_VIDEO_PLL1_BYPASS … #define IMX8MM_DRAM_PLL_BYPASS … #define IMX8MM_GPU_PLL_BYPASS … #define IMX8MM_VPU_PLL_BYPASS … #define IMX8MM_ARM_PLL_BYPASS … #define IMX8MM_SYS_PLL1_BYPASS … #define IMX8MM_SYS_PLL2_BYPASS … #define IMX8MM_SYS_PLL3_BYPASS … #define IMX8MM_AUDIO_PLL1_OUT … #define IMX8MM_AUDIO_PLL2_OUT … #define IMX8MM_VIDEO_PLL1_OUT … #define IMX8MM_DRAM_PLL_OUT … #define IMX8MM_GPU_PLL_OUT … #define IMX8MM_VPU_PLL_OUT … #define IMX8MM_ARM_PLL_OUT … #define IMX8MM_SYS_PLL1_OUT … #define IMX8MM_SYS_PLL2_OUT … #define IMX8MM_SYS_PLL3_OUT … #define IMX8MM_SYS_PLL1_40M … #define IMX8MM_SYS_PLL1_80M … #define IMX8MM_SYS_PLL1_100M … #define IMX8MM_SYS_PLL1_133M … #define IMX8MM_SYS_PLL1_160M … #define IMX8MM_SYS_PLL1_200M … #define IMX8MM_SYS_PLL1_266M … #define IMX8MM_SYS_PLL1_400M … #define IMX8MM_SYS_PLL1_800M … #define IMX8MM_SYS_PLL2_50M … #define IMX8MM_SYS_PLL2_100M … #define IMX8MM_SYS_PLL2_125M … #define IMX8MM_SYS_PLL2_166M … #define IMX8MM_SYS_PLL2_200M … #define IMX8MM_SYS_PLL2_250M … #define IMX8MM_SYS_PLL2_333M … #define IMX8MM_SYS_PLL2_500M … #define IMX8MM_SYS_PLL2_1000M … /* core */ #define IMX8MM_CLK_A53_SRC … #define IMX8MM_CLK_M4_SRC … #define IMX8MM_CLK_VPU_SRC … #define IMX8MM_CLK_GPU3D_SRC … #define IMX8MM_CLK_GPU2D_SRC … #define IMX8MM_CLK_A53_CG … #define IMX8MM_CLK_M4_CG … #define IMX8MM_CLK_VPU_CG … #define IMX8MM_CLK_GPU3D_CG … #define IMX8MM_CLK_GPU2D_CG … #define IMX8MM_CLK_A53_DIV … #define IMX8MM_CLK_M4_DIV … #define IMX8MM_CLK_VPU_DIV … #define IMX8MM_CLK_GPU3D_DIV … #define IMX8MM_CLK_GPU2D_DIV … /* bus */ #define IMX8MM_CLK_MAIN_AXI … #define IMX8MM_CLK_ENET_AXI … #define IMX8MM_CLK_NAND_USDHC_BUS … #define IMX8MM_CLK_VPU_BUS … #define IMX8MM_CLK_DISP_AXI … #define IMX8MM_CLK_DISP_APB … #define IMX8MM_CLK_DISP_RTRM … #define IMX8MM_CLK_USB_BUS … #define IMX8MM_CLK_GPU_AXI … #define IMX8MM_CLK_GPU_AHB … #define IMX8MM_CLK_NOC … #define IMX8MM_CLK_NOC_APB … #define IMX8MM_CLK_AHB … #define IMX8MM_CLK_AUDIO_AHB … #define IMX8MM_CLK_IPG_ROOT … #define IMX8MM_CLK_IPG_AUDIO_ROOT … #define IMX8MM_CLK_DRAM_ALT … #define IMX8MM_CLK_DRAM_APB … #define IMX8MM_CLK_VPU_G1 … #define IMX8MM_CLK_VPU_G2 … #define IMX8MM_CLK_DISP_DTRC … #define IMX8MM_CLK_DISP_DC8000 … #define IMX8MM_CLK_PCIE1_CTRL … #define IMX8MM_CLK_PCIE1_PHY … #define IMX8MM_CLK_PCIE1_AUX … #define IMX8MM_CLK_DC_PIXEL … #define IMX8MM_CLK_LCDIF_PIXEL … #define IMX8MM_CLK_SAI1 … #define IMX8MM_CLK_SAI2 … #define IMX8MM_CLK_SAI3 … #define IMX8MM_CLK_SAI4 … #define IMX8MM_CLK_SAI5 … #define IMX8MM_CLK_SAI6 … #define IMX8MM_CLK_SPDIF1 … #define IMX8MM_CLK_SPDIF2 … #define IMX8MM_CLK_ENET_REF … #define IMX8MM_CLK_ENET_TIMER … #define IMX8MM_CLK_ENET_PHY_REF … #define IMX8MM_CLK_NAND … #define IMX8MM_CLK_QSPI … #define IMX8MM_CLK_USDHC1 … #define IMX8MM_CLK_USDHC2 … #define IMX8MM_CLK_I2C1 … #define IMX8MM_CLK_I2C2 … #define IMX8MM_CLK_I2C3 … #define IMX8MM_CLK_I2C4 … #define IMX8MM_CLK_UART1 … #define IMX8MM_CLK_UART2 … #define IMX8MM_CLK_UART3 … #define IMX8MM_CLK_UART4 … #define IMX8MM_CLK_USB_CORE_REF … #define IMX8MM_CLK_USB_PHY_REF … #define IMX8MM_CLK_ECSPI1 … #define IMX8MM_CLK_ECSPI2 … #define IMX8MM_CLK_PWM1 … #define IMX8MM_CLK_PWM2 … #define IMX8MM_CLK_PWM3 … #define IMX8MM_CLK_PWM4 … #define IMX8MM_CLK_GPT1 … #define IMX8MM_CLK_WDOG … #define IMX8MM_CLK_WRCLK … #define IMX8MM_CLK_DSI_CORE … #define IMX8MM_CLK_DSI_PHY_REF … #define IMX8MM_CLK_DSI_DBI … #define IMX8MM_CLK_USDHC3 … #define IMX8MM_CLK_CSI1_CORE … #define IMX8MM_CLK_CSI1_PHY_REF … #define IMX8MM_CLK_CSI1_ESC … #define IMX8MM_CLK_CSI2_CORE … #define IMX8MM_CLK_CSI2_PHY_REF … #define IMX8MM_CLK_CSI2_ESC … #define IMX8MM_CLK_PCIE2_CTRL … #define IMX8MM_CLK_PCIE2_PHY … #define IMX8MM_CLK_PCIE2_AUX … #define IMX8MM_CLK_ECSPI3 … #define IMX8MM_CLK_PDM … #define IMX8MM_CLK_VPU_H1 … #define IMX8MM_CLK_CLKO1 … #define IMX8MM_CLK_ECSPI1_ROOT … #define IMX8MM_CLK_ECSPI2_ROOT … #define IMX8MM_CLK_ECSPI3_ROOT … #define IMX8MM_CLK_ENET1_ROOT … #define IMX8MM_CLK_GPT1_ROOT … #define IMX8MM_CLK_I2C1_ROOT … #define IMX8MM_CLK_I2C2_ROOT … #define IMX8MM_CLK_I2C3_ROOT … #define IMX8MM_CLK_I2C4_ROOT … #define IMX8MM_CLK_OCOTP_ROOT … #define IMX8MM_CLK_PCIE1_ROOT … #define IMX8MM_CLK_PWM1_ROOT … #define IMX8MM_CLK_PWM2_ROOT … #define IMX8MM_CLK_PWM3_ROOT … #define IMX8MM_CLK_PWM4_ROOT … #define IMX8MM_CLK_QSPI_ROOT … #define IMX8MM_CLK_NAND_ROOT … #define IMX8MM_CLK_SAI1_ROOT … #define IMX8MM_CLK_SAI1_IPG … #define IMX8MM_CLK_SAI2_ROOT … #define IMX8MM_CLK_SAI2_IPG … #define IMX8MM_CLK_SAI3_ROOT … #define IMX8MM_CLK_SAI3_IPG … #define IMX8MM_CLK_SAI4_ROOT … #define IMX8MM_CLK_SAI4_IPG … #define IMX8MM_CLK_SAI5_ROOT … #define IMX8MM_CLK_SAI5_IPG … #define IMX8MM_CLK_SAI6_ROOT … #define IMX8MM_CLK_SAI6_IPG … #define IMX8MM_CLK_UART1_ROOT … #define IMX8MM_CLK_UART2_ROOT … #define IMX8MM_CLK_UART3_ROOT … #define IMX8MM_CLK_UART4_ROOT … #define IMX8MM_CLK_USB1_CTRL_ROOT … #define IMX8MM_CLK_GPU3D_ROOT … #define IMX8MM_CLK_USDHC1_ROOT … #define IMX8MM_CLK_USDHC2_ROOT … #define IMX8MM_CLK_WDOG1_ROOT … #define IMX8MM_CLK_WDOG2_ROOT … #define IMX8MM_CLK_WDOG3_ROOT … #define IMX8MM_CLK_VPU_G1_ROOT … #define IMX8MM_CLK_GPU_BUS_ROOT … #define IMX8MM_CLK_VPU_H1_ROOT … #define IMX8MM_CLK_VPU_G2_ROOT … #define IMX8MM_CLK_PDM_ROOT … #define IMX8MM_CLK_DISP_ROOT … #define IMX8MM_CLK_DISP_AXI_ROOT … #define IMX8MM_CLK_DISP_APB_ROOT … #define IMX8MM_CLK_DISP_RTRM_ROOT … #define IMX8MM_CLK_USDHC3_ROOT … #define IMX8MM_CLK_TMU_ROOT … #define IMX8MM_CLK_VPU_DEC_ROOT … #define IMX8MM_CLK_SDMA1_ROOT … #define IMX8MM_CLK_SDMA2_ROOT … #define IMX8MM_CLK_SDMA3_ROOT … #define IMX8MM_CLK_GPT_3M … #define IMX8MM_CLK_ARM … #define IMX8MM_CLK_PDM_IPG … #define IMX8MM_CLK_GPU2D_ROOT … #define IMX8MM_CLK_MU_ROOT … #define IMX8MM_CLK_CSI1_ROOT … #define IMX8MM_CLK_DRAM_CORE … #define IMX8MM_CLK_DRAM_ALT_ROOT … #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK … #define IMX8MM_CLK_GPIO1_ROOT … #define IMX8MM_CLK_GPIO2_ROOT … #define IMX8MM_CLK_GPIO3_ROOT … #define IMX8MM_CLK_GPIO4_ROOT … #define IMX8MM_CLK_GPIO5_ROOT … #define IMX8MM_CLK_SNVS_ROOT … #define IMX8MM_CLK_GIC … #define IMX8MM_SYS_PLL1_40M_CG … #define IMX8MM_SYS_PLL1_80M_CG … #define IMX8MM_SYS_PLL1_100M_CG … #define IMX8MM_SYS_PLL1_133M_CG … #define IMX8MM_SYS_PLL1_160M_CG … #define IMX8MM_SYS_PLL1_200M_CG … #define IMX8MM_SYS_PLL1_266M_CG … #define IMX8MM_SYS_PLL1_400M_CG … #define IMX8MM_SYS_PLL2_50M_CG … #define IMX8MM_SYS_PLL2_100M_CG … #define IMX8MM_SYS_PLL2_125M_CG … #define IMX8MM_SYS_PLL2_166M_CG … #define IMX8MM_SYS_PLL2_200M_CG … #define IMX8MM_SYS_PLL2_250M_CG … #define IMX8MM_SYS_PLL2_333M_CG … #define IMX8MM_SYS_PLL2_500M_CG … #define IMX8MM_CLK_M4_CORE … #define IMX8MM_CLK_VPU_CORE … #define IMX8MM_CLK_GPU3D_CORE … #define IMX8MM_CLK_GPU2D_CORE … #define IMX8MM_CLK_CLKO2 … #define IMX8MM_CLK_A53_CORE … #define IMX8MM_CLK_CLKOUT1_SEL … #define IMX8MM_CLK_CLKOUT1_DIV … #define IMX8MM_CLK_CLKOUT1 … #define IMX8MM_CLK_CLKOUT2_SEL … #define IMX8MM_CLK_CLKOUT2_DIV … #define IMX8MM_CLK_CLKOUT2 … #define IMX8MM_CLK_END … #endif
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