linux/drivers/clk/imx/clk-sscg-pll.c

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2018 NXP.
 *
 * This driver supports the SCCG plls found in the imx8m SOCs
 *
 * Documentation for this SCCG pll can be found at:
 *   https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
 */

#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>
#include <linux/bitfield.h>

#include "clk.h"

/* PLL CFGs */
#define PLL_CFG0 …
#define PLL_CFG1 …
#define PLL_CFG2 …

#define PLL_DIVF1_MASK …
#define PLL_DIVF2_MASK …
#define PLL_DIVR1_MASK …
#define PLL_DIVR2_MASK …
#define PLL_DIVQ_MASK …
#define PLL_REF_MASK …

#define PLL_LOCK_MASK …
#define PLL_PD_MASK …

/* These are the specification limits for the SSCG PLL */
#define PLL_REF_MIN_FREQ …
#define PLL_REF_MAX_FREQ …

#define PLL_STAGE1_MIN_FREQ …
#define PLL_STAGE1_MAX_FREQ …

#define PLL_STAGE1_REF_MIN_FREQ …
#define PLL_STAGE1_REF_MAX_FREQ …

#define PLL_STAGE2_MIN_FREQ …
#define PLL_STAGE2_MAX_FREQ …

#define PLL_STAGE2_REF_MIN_FREQ …
#define PLL_STAGE2_REF_MAX_FREQ …

#define PLL_OUT_MIN_FREQ …
#define PLL_OUT_MAX_FREQ …

#define PLL_DIVR1_MAX …
#define PLL_DIVR2_MAX …
#define PLL_DIVF1_MAX …
#define PLL_DIVF2_MAX …
#define PLL_DIVQ_MAX …

#define PLL_BYPASS_NONE …
#define PLL_BYPASS1 …
#define PLL_BYPASS2 …

#define SSCG_PLL_BYPASS1_MASK …
#define SSCG_PLL_BYPASS2_MASK …
#define SSCG_PLL_BYPASS_MASK …

#define PLL_SCCG_LOCK_TIMEOUT …

struct clk_sscg_pll_setup { … };

struct clk_sscg_pll { … };

#define to_clk_sscg_pll(_hw) …

static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll)
{ … }

static int clk_sscg_pll2_check_match(struct clk_sscg_pll_setup *setup,
					struct clk_sscg_pll_setup *temp_setup)
{ … }

static int clk_sscg_divq_lookup(struct clk_sscg_pll_setup *setup,
				struct clk_sscg_pll_setup *temp_setup)
{ … }

static int clk_sscg_divf2_lookup(struct clk_sscg_pll_setup *setup,
					struct clk_sscg_pll_setup *temp_setup)
{ … }

static int clk_sscg_divr2_lookup(struct clk_sscg_pll_setup *setup,
				struct clk_sscg_pll_setup *temp_setup)
{ … }

static int clk_sscg_pll2_find_setup(struct clk_sscg_pll_setup *setup,
					struct clk_sscg_pll_setup *temp_setup,
					uint64_t ref)
{ … }

static int clk_sscg_divf1_lookup(struct clk_sscg_pll_setup *setup,
				struct clk_sscg_pll_setup *temp_setup)
{ … }

static int clk_sscg_divr1_lookup(struct clk_sscg_pll_setup *setup,
				struct clk_sscg_pll_setup *temp_setup)
{ … }

static int clk_sscg_pll1_find_setup(struct clk_sscg_pll_setup *setup,
					struct clk_sscg_pll_setup *temp_setup,
					uint64_t ref)
{ … }

static int clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup,
					uint64_t prate,
					uint64_t rate, int try_bypass)
{ … }

static int clk_sscg_pll_is_prepared(struct clk_hw *hw)
{ … }

static int clk_sscg_pll_prepare(struct clk_hw *hw)
{ … }

static void clk_sscg_pll_unprepare(struct clk_hw *hw)
{ … }

static unsigned long clk_sscg_pll_recalc_rate(struct clk_hw *hw,
					 unsigned long parent_rate)
{ … }

static int clk_sscg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
			    unsigned long parent_rate)
{ … }

static u8 clk_sscg_pll_get_parent(struct clk_hw *hw)
{ … }

static int clk_sscg_pll_set_parent(struct clk_hw *hw, u8 index)
{ … }

static int __clk_sscg_pll_determine_rate(struct clk_hw *hw,
					struct clk_rate_request *req,
					uint64_t min,
					uint64_t max,
					uint64_t rate,
					int bypass)
{ … }

static int clk_sscg_pll_determine_rate(struct clk_hw *hw,
				       struct clk_rate_request *req)
{ … }

static const struct clk_ops clk_sscg_pll_ops = …;

struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
				const char * const *parent_names,
				u8 num_parents,
				u8 parent, u8 bypass1, u8 bypass2,
				void __iomem *base,
				unsigned long flags)
{ … }
EXPORT_SYMBOL_GPL(…);