linux/drivers/clk/imx/clk-pfdv2.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017~2018 NXP
 *
 * Author: Dong Aisheng <[email protected]>
 *
 */

#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/slab.h>

#include "clk.h"

/**
 * struct clk_pfdv2 - IMX PFD clock
 * @hw:		clock source
 * @reg:	PFD register address
 * @gate_bit:	Gate bit offset
 * @vld_bit:	Valid bit offset
 * @frac_off:	PLL Fractional Divider offset
 */

struct clk_pfdv2 { … };

#define to_clk_pfdv2(_hw) …

#define CLK_PFDV2_FRAC_MASK …

#define LOCK_TIMEOUT_US …

static DEFINE_SPINLOCK(pfd_lock);

static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
{ … }

static int clk_pfdv2_enable(struct clk_hw *hw)
{ … }

static void clk_pfdv2_disable(struct clk_hw *hw)
{ … }

static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
					   unsigned long parent_rate)
{ … }

static int clk_pfdv2_determine_rate(struct clk_hw *hw,
				    struct clk_rate_request *req)
{ … }

static int clk_pfdv2_is_enabled(struct clk_hw *hw)
{ … }

static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
			      unsigned long parent_rate)
{ … }

static const struct clk_ops clk_pfdv2_ops = …;

struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
			     const char *parent_name, void __iomem *reg, u8 idx)
{ … }
EXPORT_SYMBOL_GPL(…);