/* * Copyright (c) 2013 - 2017 Intel Corporation. All rights reserved. * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation. * All rights reserved. * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ /* * This file contains all of the code that is specific to the * QLogic_IB 6120 PCIe chip. */ #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/delay.h> #include <rdma/ib_verbs.h> #include "qib.h" #include "qib_6120_regs.h" static void qib_6120_setup_setextled(struct qib_pportdata *, u32); static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op); static u8 qib_6120_phys_portstate(u64); static u32 qib_6120_iblink_state(u64); /* * This file contains all the chip-specific register information and * access functions for the Intel Intel_IB PCI-Express chip. * */ /* KREG_IDX uses machine-generated #defines */ #define KREG_IDX(regname) … /* Use defines to tie machine-generated names to lower-case names */ #define kr_extctrl … #define kr_extstatus … #define kr_gpio_clear … #define kr_gpio_mask … #define kr_gpio_out … #define kr_gpio_status … #define kr_rcvctrl … #define kr_sendctrl … #define kr_partitionkey … #define kr_hwdiagctrl … #define kr_ibcstatus … #define kr_ibcctrl … #define kr_sendbuffererror … #define kr_rcvbthqp … #define kr_counterregbase … #define kr_palign … #define kr_rcvegrbase … #define kr_rcvegrcnt … #define kr_rcvhdrcnt … #define kr_rcvhdrentsize … #define kr_rcvhdrsize … #define kr_rcvtidbase … #define kr_rcvtidcnt … #define kr_scratch … #define kr_sendctrl … #define kr_sendpioavailaddr … #define kr_sendpiobufbase … #define kr_sendpiobufcnt … #define kr_sendpiosize … #define kr_sendregbase … #define kr_userregbase … #define kr_control … #define kr_intclear … #define kr_intmask … #define kr_intstatus … #define kr_errclear … #define kr_errmask … #define kr_errstatus … #define kr_hwerrclear … #define kr_hwerrmask … #define kr_hwerrstatus … #define kr_revision … #define kr_portcnt … #define kr_serdes_cfg0 … #define kr_serdes_cfg1 … #define kr_serdes_stat … #define kr_xgxs_cfg … /* These must only be written via qib_write_kreg_ctxt() */ #define kr_rcvhdraddr … #define kr_rcvhdrtailaddr … #define CREG_IDX(regname) … #define cr_badformat … #define cr_erricrc … #define cr_errlink … #define cr_errlpcrc … #define cr_errpkey … #define cr_rcvflowctrl_err … #define cr_err_rlen … #define cr_errslen … #define cr_errtidfull … #define cr_errtidvalid … #define cr_errvcrc … #define cr_ibstatuschange … #define cr_lbint … #define cr_invalidrlen … #define cr_invalidslen … #define cr_lbflowstall … #define cr_pktrcv … #define cr_pktrcvflowctrl … #define cr_pktsend … #define cr_pktsendflow … #define cr_portovfl … #define cr_rcvebp … #define cr_rcvovfl … #define cr_senddropped … #define cr_sendstall … #define cr_sendunderrun … #define cr_wordrcv … #define cr_wordsend … #define cr_txunsupvl … #define cr_rxdroppkt … #define cr_iblinkerrrecov … #define cr_iblinkdown … #define cr_ibsymbolerr … #define SYM_RMASK(regname, fldname) … #define SYM_MASK(regname, fldname) … #define SYM_LSB(regname, fldname) … #define SYM_FIELD(value, regname, fldname) … #define ERR_MASK(fldname) … #define HWE_MASK(fldname) … /* link training states, from IBC */ #define IB_6120_LT_STATE_DISABLED … #define IB_6120_LT_STATE_LINKUP … #define IB_6120_LT_STATE_POLLACTIVE … #define IB_6120_LT_STATE_POLLQUIET … #define IB_6120_LT_STATE_SLEEPDELAY … #define IB_6120_LT_STATE_SLEEPQUIET … #define IB_6120_LT_STATE_CFGDEBOUNCE … #define IB_6120_LT_STATE_CFGRCVFCFG … #define IB_6120_LT_STATE_CFGWAITRMT … #define IB_6120_LT_STATE_CFGIDLE … #define IB_6120_LT_STATE_RECOVERRETRAIN … #define IB_6120_LT_STATE_RECOVERWAITRMT … #define IB_6120_LT_STATE_RECOVERIDLE … /* link state machine states from IBC */ #define IB_6120_L_STATE_DOWN … #define IB_6120_L_STATE_INIT … #define IB_6120_L_STATE_ARM … #define IB_6120_L_STATE_ACTIVE … #define IB_6120_L_STATE_ACT_DEFER … static const u8 qib_6120_physportstate[0x20] = …; struct qib_chip_specific { … }; /* ibcctrl bits */ #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE … /* cycle through TS1/TS2 till OK */ #define QLOGIC_IB_IBCC_LINKINITCMD_POLL … /* wait for TS1, then go on */ #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP … #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT … #define QLOGIC_IB_IBCC_LINKCMD_DOWN … #define QLOGIC_IB_IBCC_LINKCMD_ARMED … #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE … #define QLOGIC_IB_IBCC_LINKCMD_SHIFT … /* * We could have a single register get/put routine, that takes a group type, * but this is somewhat clearer and cleaner. It also gives us some error * checking. 64 bit register reads should always work, but are inefficient * on opteron (the northbridge always generates 2 separate HT 32 bit reads), * so we use kreg32 wherever possible. User register and counter register * reads are always 32 bit reads, so only one form of those routines. */ /** * qib_read_ureg32 - read 32-bit virtualized per-context register * @dd: device * @regno: register number * @ctxt: context number * * Return the contents of a register that is virtualized to be per context. * Returns -1 on errors (not distinguishable from valid contents at * runtime; we may add a separate error variable at some point). */ static inline u32 qib_read_ureg32(const struct qib_devdata *dd, enum qib_ureg regno, int ctxt) { … } /** * qib_write_ureg - write 32-bit virtualized per-context register * @dd: device * @regno: register number * @value: value * @ctxt: context * * Write the contents of a register that is virtualized to be per context. */ static inline void qib_write_ureg(const struct qib_devdata *dd, enum qib_ureg regno, u64 value, int ctxt) { … } static inline u32 qib_read_kreg32(const struct qib_devdata *dd, const u16 regno) { … } static inline u64 qib_read_kreg64(const struct qib_devdata *dd, const u16 regno) { … } static inline void qib_write_kreg(const struct qib_devdata *dd, const u16 regno, u64 value) { … } /** * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register * @dd: the qlogic_ib device * @regno: the register number to write * @ctxt: the context containing the register * @value: the value to write */ static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, const u16 regno, unsigned ctxt, u64 value) { … } static inline void write_6120_creg(const struct qib_devdata *dd, u16 regno, u64 value) { … } static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno) { … } static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno) { … } /* kr_control bits */ #define QLOGIC_IB_C_RESET … /* kr_intstatus, kr_intclear, kr_intmask bits */ #define QLOGIC_IB_I_RCVURG_MASK … #define QLOGIC_IB_I_RCVURG_SHIFT … #define QLOGIC_IB_I_RCVAVAIL_MASK … #define QLOGIC_IB_I_RCVAVAIL_SHIFT … #define QLOGIC_IB_C_FREEZEMODE … #define QLOGIC_IB_C_LINKENABLE … #define QLOGIC_IB_I_ERROR … #define QLOGIC_IB_I_SPIOSENT … #define QLOGIC_IB_I_SPIOBUFAVAIL … #define QLOGIC_IB_I_GPIO … #define QLOGIC_IB_I_BITSEXTANT … /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */ #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK … #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT … #define QLOGIC_IB_HWE_PCIEPOISONEDTLP … #define QLOGIC_IB_HWE_PCIECPLTIMEOUT … #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH … #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM … #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM … #define QLOGIC_IB_HWE_COREPLL_FBSLIP … #define QLOGIC_IB_HWE_COREPLL_RFSLIP … #define QLOGIC_IB_HWE_PCIE1PLLFAILED … #define QLOGIC_IB_HWE_PCIE0PLLFAILED … #define QLOGIC_IB_HWE_SERDESPLLFAILED … /* kr_extstatus bits */ #define QLOGIC_IB_EXTS_FREQSEL … #define QLOGIC_IB_EXTS_SERDESSEL … #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST … #define QLOGIC_IB_EXTS_MEMBIST_FOUND … /* kr_xgxsconfig bits */ #define QLOGIC_IB_XGXS_RESET … #define _QIB_GPIO_SDA_NUM … #define _QIB_GPIO_SCL_NUM … /* Bits in GPIO for the added IB link interrupts */ #define GPIO_RXUVL_BIT … #define GPIO_OVRUN_BIT … #define GPIO_LLI_BIT … #define GPIO_ERRINTR_MASK … #define QLOGIC_IB_RT_BUFSIZE_MASK … #define QLOGIC_IB_RT_BUFSIZE_SHIFTVAL(tid) … #define QLOGIC_IB_RT_BUFSIZE(tid) … #define QLOGIC_IB_RT_IS_VALID(tid) … #define QLOGIC_IB_RT_ADDR_MASK … #define QLOGIC_IB_RT_ADDR_SHIFT … #define QLOGIC_IB_R_INTRAVAIL_SHIFT … #define QLOGIC_IB_R_TAILUPD_SHIFT … #define IBA6120_R_PKEY_DIS_SHIFT … #define PBC_6120_VL15_SEND_CTRL … #define IBCBUSFRSPCPARITYERR … #define IBCBUSTOSPCPARITYERR … #define SYM_MASK_BIT(regname, fldname, bit) … #define TXEMEMPARITYERR_PIOBUF … #define TXEMEMPARITYERR_PIOPBC … #define TXEMEMPARITYERR_PIOLAUNCHFIFO … #define RXEMEMPARITYERR_RCVBUF … #define RXEMEMPARITYERR_LOOKUPQ … #define RXEMEMPARITYERR_EXPTID … #define RXEMEMPARITYERR_EAGERTID … #define RXEMEMPARITYERR_FLAGBUF … #define RXEMEMPARITYERR_DATAINFO … #define RXEMEMPARITYERR_HDRINFO … /* 6120 specific hardware errors... */ static const struct qib_hwerror_msgs qib_6120_hwerror_msgs[] = …; #define TXE_PIO_PARITY … #define _QIB_PLL_FAIL … /* variables for sanity checking interrupt and errors */ #define IB_HWE_BITSEXTANT … #define IB_E_BITSEXTANT … #define QLOGIC_IB_E_PKTERRS … /* These are all rcv-related errors which we want to count for stats */ #define E_SUM_PKTERRS … /* These are all send-related errors which we want to count for stats */ #define E_SUM_ERRS … /* * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore * errors not related to freeze and cancelling buffers. Can't ignore * armlaunch because could get more while still cleaning up, and need * to cancel those as they happen. */ #define E_SPKT_ERRS_IGNORE … /* * these are errors that can occur when the link changes state while * a packet is being sent or received. This doesn't cover things * like EBP or VCRC that can be the result of a sending having the * link change state, so we receive a "known bad" packet. */ #define E_SUM_LINK_PKTERRS … static void qib_6120_put_tid_2(struct qib_devdata *, u64 __iomem *, u32, unsigned long); /* * On platforms using this chip, and not having ordered WC stores, we * can get TXE parity errors due to speculative reads to the PIO buffers, * and this, due to a chip issue can result in (many) false parity error * reports. So it's a debug print on those, and an info print on systems * where the speculative reads don't occur. */ static void qib_6120_txe_recover(struct qib_devdata *dd) { … } /* enable/disable chip from delivering interrupts */ static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable) { … } /* * Try to cleanup as much as possible for anything that might have gone * wrong while in freeze mode, such as pio buffers being written by user * processes (causing armlaunch), send errors due to going into freeze mode, * etc., and try to avoid causing extra interrupts while doing so. * Forcibly update the in-memory pioavail register copies after cleanup * because the chip won't do it while in freeze mode (the register values * themselves are kept correct). * Make sure that we don't lose any important interrupts by using the chip * feature that says that writing 0 to a bit in *clear that is set in * *status will cause an interrupt to be generated again (if allowed by * the *mask value). * This is in chip-specific code because of all of the register accesses, * even though the details are similar on most chips */ static void qib_6120_clear_freeze(struct qib_devdata *dd) { … } /** * qib_handle_6120_hwerrors - display hardware errors. * @dd: the qlogic_ib device * @msg: the output buffer * @msgl: the size of the output buffer * * Use same msg buffer as regular errors to avoid excessive stack * use. Most hardware errors are catastrophic, but for right now, * we'll print them and continue. Reuse the same message buffer as * handle_6120_errors() to avoid excessive stack usage. */ static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg, size_t msgl) { … } /* * Decode the error status into strings, deciding whether to always * print * it or not depending on "normal packet errors" vs everything * else. Return 1 if "real" errors, otherwise 0 if only packet * errors, so caller can decide what to print with the string. */ static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err) { … } /* * Called when we might have an error that is specific to a particular * PIO buffer, and may need to cancel that buffer, so it can be re-used. */ static void qib_disarm_6120_senderrbufs(struct qib_pportdata *ppd) { … } static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs) { … } static void handle_6120_errors(struct qib_devdata *dd, u64 errs) { … } /** * qib_6120_init_hwerrors - enable hardware errors * @dd: the qlogic_ib device * * now that we have finished initializing everything that might reasonably * cause a hardware error, and cleared those errors bits as they occur, * we can enable hardware errors in the mask (potentially enabling * freeze mode), and enable hardware errors as errors (along with * everything else) in errormask */ static void qib_6120_init_hwerrors(struct qib_devdata *dd) { … } /* * Disable and enable the armlaunch error. Used for PIO bandwidth testing * on chips that are count-based, rather than trigger-based. There is no * reference counting, but that's also fine, given the intended use. * Only chip-specific because it's all register accesses */ static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable) { … } /* * Formerly took parameter <which> in pre-shifted, * pre-merged form with LinkCmd and LinkInitCmd * together, and assuming the zero was NOP. */ static void qib_set_ib_6120_lstate(struct qib_pportdata *ppd, u16 linkcmd, u16 linitcmd) { … } /** * qib_6120_bringup_serdes - bring up the serdes * @ppd: the qlogic_ib device */ static int qib_6120_bringup_serdes(struct qib_pportdata *ppd) { … } /** * qib_6120_quiet_serdes - set serdes to txidle * @ppd: physical port of the qlogic_ib device * Called when driver is being unloaded */ static void qib_6120_quiet_serdes(struct qib_pportdata *ppd) { … } /** * qib_6120_setup_setextled - set the state of the two external LEDs * @ppd: the qlogic_ib device * @on: whether the link is up or not * * The exact combo of LEDs if on is true is determined by looking * at the ibcstatus. * These LEDs indicate the physical and logical state of IB link. * For this chip (at least with recommended board pinouts), LED1 * is Yellow (logical state) and LED2 is Green (physical state), * * Note: We try to match the Mellanox HCA LED behavior as best * we can. Green indicates physical link state is OK (something is * plugged in, and we can train). * Amber indicates the link is logically up (ACTIVE). * Mellanox further blinks the amber LED to indicate data packet * activity, but we have no hardware support for that, so it would * require waking up every 10-20 msecs and checking the counters * on the chip, and then turning the LED off if appropriate. That's * visible overhead, so not something we will do. * */ static void qib_6120_setup_setextled(struct qib_pportdata *ppd, u32 on) { … } /** * qib_6120_setup_cleanup - clean up any per-chip chip-specific stuff * @dd: the qlogic_ib device * * This is called during driver unload. */ static void qib_6120_setup_cleanup(struct qib_devdata *dd) { … } static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint) { … } /* * handle errors and unusual events first, separate function * to improve cache hits for fast path interrupt handling */ static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat) { … } static irqreturn_t qib_6120intr(int irq, void *data) { … } /* * Set up our chip-specific interrupt handler * The interrupt type has already been setup, so * we just need to do the registration and error checking. */ static void qib_setup_6120_interrupt(struct qib_devdata *dd) { … } /** * pe_boardname - fill in the board name * @dd: the qlogic_ib device * * info is based on the board revision register */ static void pe_boardname(struct qib_devdata *dd) { … } /* * This routine sleeps, so it can only be called from user context, not * from interrupt context. If we need interrupt context, we can split * it into two routines. */ static int qib_6120_setup_reset(struct qib_devdata *dd) { … } /** * qib_6120_put_tid - write a TID in chip * @dd: the qlogic_ib device * @tidptr: pointer to the expected TID (in chip) to update * @type: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) * for expected * @pa: physical address of in memory buffer; tidinvalid if freeing * * This exists as a separate routine to allow for special locking etc. * It's used for both the full cleanup on exit, as well as the normal * setup and teardown. */ static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, u32 type, unsigned long pa) { … } /** * qib_6120_put_tid_2 - write a TID in chip, Revision 2 or higher * @dd: the qlogic_ib device * @tidptr: pointer to the expected TID (in chip) to update * @type: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) * for expected * @pa: physical address of in memory buffer; tidinvalid if freeing * * This exists as a separate routine to allow for selection of the * appropriate "flavor". The static calls in cleanup just use the * revision-agnostic form, as they are not performance critical. */ static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr, u32 type, unsigned long pa) { … } /** * qib_6120_clear_tids - clear all TID entries for a context, expected and eager * @dd: the qlogic_ib device * @rcd: the context * * clear all TID entries for a context, expected and eager. * Used from qib_close(). On this chip, TIDs are only 32 bits, * not 64, but they are still on 64 bit boundaries, so tidbase * is declared as u64 * for the pointer math, even though we write 32 bits */ static void qib_6120_clear_tids(struct qib_devdata *dd, struct qib_ctxtdata *rcd) { … } /** * qib_6120_tidtemplate - setup constants for TID updates * @dd: the qlogic_ib device * * We setup stuff that we use a lot, to avoid calculating each time */ static void qib_6120_tidtemplate(struct qib_devdata *dd) { … } int __attribute__((weak)) qib_unordered_wc(void) { … } /** * qib_6120_get_base_info - set chip-specific flags for user code * @rcd: the qlogic_ib ctxt * @kinfo: qib_base_info pointer * * We set the PCIE flag because the lower bandwidth on PCIe vs * HyperTransport can affect some user packet algorithms. */ static int qib_6120_get_base_info(struct qib_ctxtdata *rcd, struct qib_base_info *kinfo) { … } static struct qib_message_header * qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) { … } static void qib_6120_config_ctxts(struct qib_devdata *dd) { … } static void qib_update_6120_usrhead(struct qib_ctxtdata *rcd, u64 hd, u32 updegr, u32 egrhd, u32 npkts) { … } static u32 qib_6120_hdrqempty(struct qib_ctxtdata *rcd) { … } /* * Used when we close any ctxt, for DMA already in flight * at close. Can't be done until we know hdrq size, so not * early in chip init. */ static void alloc_dummy_hdrq(struct qib_devdata *dd) { … } /* * Modify the RCVCTRL register in chip-specific way. This * is a function because bit positions and (future) register * location is chip-specific, but the needed operations are * generic. <op> is a bit-mask because we often want to * do multiple modifications. */ static void rcvctrl_6120_mod(struct qib_pportdata *ppd, unsigned int op, int ctxt) { … } /* * Modify the SENDCTRL register in chip-specific way. This * is a function there may be multiple such registers with * slightly different layouts. Only operations actually used * are implemented yet. * Chip requires no back-back sendctrl writes, so write * scratch register after writing sendctrl */ static void sendctrl_6120_mod(struct qib_pportdata *ppd, u32 op) { … } /** * qib_portcntr_6120 - read a per-port counter * @ppd: the qlogic_ib device * @reg: the counter to snapshot */ static u64 qib_portcntr_6120(struct qib_pportdata *ppd, u32 reg) { … } /* * Device counter names (not port-specific), one line per stat, * single string. Used by utilities like ipathstats to print the stats * in a way which works for different versions of drivers, without changing * the utility. Names need to be 12 chars or less (w/o newline), for proper * display by utility. * Non-error counters are first. * Start of "error" conters is indicated by a leading "E " on the first * "error" counter, and doesn't count in label length. * The EgrOvfl list needs to be last so we truncate them at the configured * context count for the device. * cntr6120indices contains the corresponding register indices. */ static const char cntr6120names[] = …; static const size_t cntr6120indices[] = …; /* * same as cntr6120names and cntr6120indices, but for port-specific counters. * portcntr6120indices is somewhat complicated by some registers needing * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG */ static const char portcntr6120names[] = … ; #define _PORT_VIRT_FLAG … static const size_t portcntr6120indices[] = …; /* do all the setup to make the counter reads efficient later */ static void init_6120_cntrnames(struct qib_devdata *dd) { … } static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep, u64 **cntrp) { … } static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, char **namep, u64 **cntrp) { … } static void qib_chk_6120_errormask(struct qib_devdata *dd) { … } /** * qib_get_6120_faststats - get word counters from chip before they overflow * @t: contains a pointer to the qlogic_ib device qib_devdata * * This needs more work; in particular, decision on whether we really * need traffic_wds done the way it is * called from add_timer */ static void qib_get_6120_faststats(struct timer_list *t) { … } /* no interrupt fallback for these chips */ static int qib_6120_nointr_fallback(struct qib_devdata *dd) { … } /* * reset the XGXS (between serdes and IBC). Slightly less intrusive * than resetting the IBC or external link state, and useful in some * cases to cause some retraining. To do this right, we reset IBC * as well. */ static void qib_6120_xgxs_reset(struct qib_pportdata *ppd) { … } static int qib_6120_get_ib_cfg(struct qib_pportdata *ppd, int which) { … } /* * We assume range checking is already done, if needed. */ static int qib_6120_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) { … } static int qib_6120_set_loopback(struct qib_pportdata *ppd, const char *what) { … } static void pma_6120_timer(struct timer_list *t) { … } /* * Note that the caller has the ibp->rvp.lock held. */ static void qib_set_cntr_6120_sample(struct qib_pportdata *ppd, u32 intv, u32 start) { … } static u32 qib_6120_iblink_state(u64 ibcs) { … } /* returns the IBTA port state, rather than the IBC link training state */ static u8 qib_6120_phys_portstate(u64 ibcs) { … } static int qib_6120_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) { … } /* Does read/modify/write to appropriate registers to * set output and direction bits selected by mask. * these are in their canonical positions (e.g. lsb of * dir will end up in D48 of extctrl on existing chips). * returns contents of GP Inputs. */ static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) { … } /* * Read fundamental info we need to use the chip. These are * the registers that describe chip capabilities, and are * saved in shadow registers. */ static void get_6120_chip_params(struct qib_devdata *dd) { … } /* * The chip base addresses in cspec and cpspec have to be set * after possible init_chip_wc_pat(), rather than in * get_6120_chip_params(), so split out as separate function */ static void set_6120_baseaddrs(struct qib_devdata *dd) { … } /* * Write the final few registers that depend on some of the * init setup. Done late in init, just before bringing up * the serdes. */ static int qib_late_6120_initreg(struct qib_devdata *dd) { … } static int init_6120_variables(struct qib_devdata *dd) { … } /* * For this chip, we want to use the same buffer every time * when we are trying to bring the link up (they are always VL15 * packets). At that link state the packet should always go out immediately * (or at least be discarded at the tx interface if the link is down). * If it doesn't, and the buffer isn't available, that means some other * sender has gotten ahead of us, and is preventing our packet from going * out. In that case, we flush all packets, and try again. If that still * fails, we fail the request, and hope things work the next time around. * * We don't need very complicated heuristics on whether the packet had * time to go out or not, since even at SDR 1X, it goes out in very short * time periods, covered by the chip reads done here and as part of the * flush. */ static u32 __iomem *get_6120_link_buf(struct qib_pportdata *ppd, u32 *bnum) { … } static u32 __iomem *qib_6120_getsendbuf(struct qib_pportdata *ppd, u64 pbc, u32 *pbufnum) { … } static int init_sdma_6120_regs(struct qib_pportdata *ppd) { … } static u16 qib_sdma_6120_gethead(struct qib_pportdata *ppd) { … } static int qib_sdma_6120_busy(struct qib_pportdata *ppd) { … } static void qib_sdma_update_6120_tail(struct qib_pportdata *ppd, u16 tail) { … } static void qib_6120_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) { … } static void qib_sdma_set_6120_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) { … } /* * the pbc doesn't need a VL15 indicator, but we need it for link_buf. * The chip ignores the bit if set. */ static u32 qib_6120_setpbc_control(struct qib_pportdata *ppd, u32 plen, u8 srate, u8 vl) { … } static void qib_6120_initvl15_bufs(struct qib_devdata *dd) { … } static void qib_6120_init_ctxt(struct qib_ctxtdata *rcd) { … } static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start, u32 len, u32 avail, struct qib_ctxtdata *rcd) { … } static void writescratch(struct qib_devdata *dd, u32 val) { … } static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum) { … } #ifdef CONFIG_INFINIBAND_QIB_DCA static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event) { … } #endif /* Dummy function, as 6120 boards never disable EEPROM Write */ static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen) { … } /** * qib_init_iba6120_funcs - set up the chip-specific function pointers * @pdev: pci_dev of the qlogic_ib device * @ent: pci_device_id matching this chip * * This is global, and is called directly at init to set up the * chip-specific function pointers for later use. * * It also allocates/partially-inits the qib_devdata struct for * this device. */ struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *pdev, const struct pci_device_id *ent) { … }
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