/* * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef _T4FW_RI_API_H_ #define _T4FW_RI_API_H_ #include "t4fw_api.h" enum fw_ri_wr_opcode { … }; enum fw_ri_wr_flags { … }; enum fw_ri_mpa_attrs { … }; enum fw_ri_qp_caps { … }; enum fw_ri_addr_type { … }; enum fw_ri_mem_perms { … }; enum fw_ri_stag_type { … }; enum fw_ri_data_op { … }; enum fw_ri_sgl_depth { … }; struct fw_ri_dsge_pair { … }; struct fw_ri_dsgl { … }; struct fw_ri_sge { … }; struct fw_ri_isgl { … }; struct fw_ri_immd { … }; struct fw_ri_tpte { … }; #define FW_RI_TPTE_VALID_S … #define FW_RI_TPTE_VALID_M … #define FW_RI_TPTE_VALID_V(x) … #define FW_RI_TPTE_VALID_G(x) … #define FW_RI_TPTE_VALID_F … #define FW_RI_TPTE_STAGKEY_S … #define FW_RI_TPTE_STAGKEY_M … #define FW_RI_TPTE_STAGKEY_V(x) … #define FW_RI_TPTE_STAGKEY_G(x) … #define FW_RI_TPTE_STAGSTATE_S … #define FW_RI_TPTE_STAGSTATE_M … #define FW_RI_TPTE_STAGSTATE_V(x) … #define FW_RI_TPTE_STAGSTATE_G(x) … #define FW_RI_TPTE_STAGSTATE_F … #define FW_RI_TPTE_STAGTYPE_S … #define FW_RI_TPTE_STAGTYPE_M … #define FW_RI_TPTE_STAGTYPE_V(x) … #define FW_RI_TPTE_STAGTYPE_G(x) … #define FW_RI_TPTE_PDID_S … #define FW_RI_TPTE_PDID_M … #define FW_RI_TPTE_PDID_V(x) … #define FW_RI_TPTE_PDID_G(x) … #define FW_RI_TPTE_PERM_S … #define FW_RI_TPTE_PERM_M … #define FW_RI_TPTE_PERM_V(x) … #define FW_RI_TPTE_PERM_G(x) … #define FW_RI_TPTE_REMINVDIS_S … #define FW_RI_TPTE_REMINVDIS_M … #define FW_RI_TPTE_REMINVDIS_V(x) … #define FW_RI_TPTE_REMINVDIS_G(x) … #define FW_RI_TPTE_REMINVDIS_F … #define FW_RI_TPTE_ADDRTYPE_S … #define FW_RI_TPTE_ADDRTYPE_M … #define FW_RI_TPTE_ADDRTYPE_V(x) … #define FW_RI_TPTE_ADDRTYPE_G(x) … #define FW_RI_TPTE_ADDRTYPE_F … #define FW_RI_TPTE_MWBINDEN_S … #define FW_RI_TPTE_MWBINDEN_M … #define FW_RI_TPTE_MWBINDEN_V(x) … #define FW_RI_TPTE_MWBINDEN_G(x) … #define FW_RI_TPTE_MWBINDEN_F … #define FW_RI_TPTE_PS_S … #define FW_RI_TPTE_PS_M … #define FW_RI_TPTE_PS_V(x) … #define FW_RI_TPTE_PS_G(x) … #define FW_RI_TPTE_QPID_S … #define FW_RI_TPTE_QPID_M … #define FW_RI_TPTE_QPID_V(x) … #define FW_RI_TPTE_QPID_G(x) … #define FW_RI_TPTE_NOSNOOP_S … #define FW_RI_TPTE_NOSNOOP_M … #define FW_RI_TPTE_NOSNOOP_V(x) … #define FW_RI_TPTE_NOSNOOP_G(x) … #define FW_RI_TPTE_NOSNOOP_F … #define FW_RI_TPTE_PBLADDR_S … #define FW_RI_TPTE_PBLADDR_M … #define FW_RI_TPTE_PBLADDR_V(x) … #define FW_RI_TPTE_PBLADDR_G(x) … #define FW_RI_TPTE_DCA_S … #define FW_RI_TPTE_DCA_M … #define FW_RI_TPTE_DCA_V(x) … #define FW_RI_TPTE_DCA_G(x) … #define FW_RI_TPTE_MWBCNT_PSTAG_S … #define FW_RI_TPTE_MWBCNT_PSTAG_M … #define FW_RI_TPTE_MWBCNT_PSTAT_V(x) … #define FW_RI_TPTE_MWBCNT_PSTAG_G(x) … enum fw_ri_res_type { … }; enum fw_ri_res_op { … }; struct fw_ri_res { … }; struct fw_ri_res_wr { … }; #define FW_RI_RES_WR_NRES_S … #define FW_RI_RES_WR_NRES_M … #define FW_RI_RES_WR_NRES_V(x) … #define FW_RI_RES_WR_NRES_G(x) … #define FW_RI_RES_WR_FETCHSZM_S … #define FW_RI_RES_WR_FETCHSZM_M … #define FW_RI_RES_WR_FETCHSZM_V(x) … #define FW_RI_RES_WR_FETCHSZM_G(x) … #define FW_RI_RES_WR_FETCHSZM_F … #define FW_RI_RES_WR_STATUSPGNS_S … #define FW_RI_RES_WR_STATUSPGNS_M … #define FW_RI_RES_WR_STATUSPGNS_V(x) … #define FW_RI_RES_WR_STATUSPGNS_G(x) … #define FW_RI_RES_WR_STATUSPGNS_F … #define FW_RI_RES_WR_STATUSPGRO_S … #define FW_RI_RES_WR_STATUSPGRO_M … #define FW_RI_RES_WR_STATUSPGRO_V(x) … #define FW_RI_RES_WR_STATUSPGRO_G(x) … #define FW_RI_RES_WR_STATUSPGRO_F … #define FW_RI_RES_WR_FETCHNS_S … #define FW_RI_RES_WR_FETCHNS_M … #define FW_RI_RES_WR_FETCHNS_V(x) … #define FW_RI_RES_WR_FETCHNS_G(x) … #define FW_RI_RES_WR_FETCHNS_F … #define FW_RI_RES_WR_FETCHRO_S … #define FW_RI_RES_WR_FETCHRO_M … #define FW_RI_RES_WR_FETCHRO_V(x) … #define FW_RI_RES_WR_FETCHRO_G(x) … #define FW_RI_RES_WR_FETCHRO_F … #define FW_RI_RES_WR_HOSTFCMODE_S … #define FW_RI_RES_WR_HOSTFCMODE_M … #define FW_RI_RES_WR_HOSTFCMODE_V(x) … #define FW_RI_RES_WR_HOSTFCMODE_G(x) … #define FW_RI_RES_WR_CPRIO_S … #define FW_RI_RES_WR_CPRIO_M … #define FW_RI_RES_WR_CPRIO_V(x) … #define FW_RI_RES_WR_CPRIO_G(x) … #define FW_RI_RES_WR_CPRIO_F … #define FW_RI_RES_WR_ONCHIP_S … #define FW_RI_RES_WR_ONCHIP_M … #define FW_RI_RES_WR_ONCHIP_V(x) … #define FW_RI_RES_WR_ONCHIP_G(x) … #define FW_RI_RES_WR_ONCHIP_F … #define FW_RI_RES_WR_PCIECHN_S … #define FW_RI_RES_WR_PCIECHN_M … #define FW_RI_RES_WR_PCIECHN_V(x) … #define FW_RI_RES_WR_PCIECHN_G(x) … #define FW_RI_RES_WR_IQID_S … #define FW_RI_RES_WR_IQID_M … #define FW_RI_RES_WR_IQID_V(x) … #define FW_RI_RES_WR_IQID_G(x) … #define FW_RI_RES_WR_DCAEN_S … #define FW_RI_RES_WR_DCAEN_M … #define FW_RI_RES_WR_DCAEN_V(x) … #define FW_RI_RES_WR_DCAEN_G(x) … #define FW_RI_RES_WR_DCAEN_F … #define FW_RI_RES_WR_DCACPU_S … #define FW_RI_RES_WR_DCACPU_M … #define FW_RI_RES_WR_DCACPU_V(x) … #define FW_RI_RES_WR_DCACPU_G(x) … #define FW_RI_RES_WR_FBMIN_S … #define FW_RI_RES_WR_FBMIN_M … #define FW_RI_RES_WR_FBMIN_V(x) … #define FW_RI_RES_WR_FBMIN_G(x) … #define FW_RI_RES_WR_FBMAX_S … #define FW_RI_RES_WR_FBMAX_M … #define FW_RI_RES_WR_FBMAX_V(x) … #define FW_RI_RES_WR_FBMAX_G(x) … #define FW_RI_RES_WR_CIDXFTHRESHO_S … #define FW_RI_RES_WR_CIDXFTHRESHO_M … #define FW_RI_RES_WR_CIDXFTHRESHO_V(x) … #define FW_RI_RES_WR_CIDXFTHRESHO_G(x) … #define FW_RI_RES_WR_CIDXFTHRESHO_F … #define FW_RI_RES_WR_CIDXFTHRESH_S … #define FW_RI_RES_WR_CIDXFTHRESH_M … #define FW_RI_RES_WR_CIDXFTHRESH_V(x) … #define FW_RI_RES_WR_CIDXFTHRESH_G(x) … #define FW_RI_RES_WR_EQSIZE_S … #define FW_RI_RES_WR_EQSIZE_M … #define FW_RI_RES_WR_EQSIZE_V(x) … #define FW_RI_RES_WR_EQSIZE_G(x) … #define FW_RI_RES_WR_IQANDST_S … #define FW_RI_RES_WR_IQANDST_M … #define FW_RI_RES_WR_IQANDST_V(x) … #define FW_RI_RES_WR_IQANDST_G(x) … #define FW_RI_RES_WR_IQANDST_F … #define FW_RI_RES_WR_IQANUS_S … #define FW_RI_RES_WR_IQANUS_M … #define FW_RI_RES_WR_IQANUS_V(x) … #define FW_RI_RES_WR_IQANUS_G(x) … #define FW_RI_RES_WR_IQANUS_F … #define FW_RI_RES_WR_IQANUD_S … #define FW_RI_RES_WR_IQANUD_M … #define FW_RI_RES_WR_IQANUD_V(x) … #define FW_RI_RES_WR_IQANUD_G(x) … #define FW_RI_RES_WR_IQANDSTINDEX_S … #define FW_RI_RES_WR_IQANDSTINDEX_M … #define FW_RI_RES_WR_IQANDSTINDEX_V(x) … #define FW_RI_RES_WR_IQANDSTINDEX_G(x) … #define FW_RI_RES_WR_IQDROPRSS_S … #define FW_RI_RES_WR_IQDROPRSS_M … #define FW_RI_RES_WR_IQDROPRSS_V(x) … #define FW_RI_RES_WR_IQDROPRSS_G(x) … #define FW_RI_RES_WR_IQDROPRSS_F … #define FW_RI_RES_WR_IQGTSMODE_S … #define FW_RI_RES_WR_IQGTSMODE_M … #define FW_RI_RES_WR_IQGTSMODE_V(x) … #define FW_RI_RES_WR_IQGTSMODE_G(x) … #define FW_RI_RES_WR_IQGTSMODE_F … #define FW_RI_RES_WR_IQPCIECH_S … #define FW_RI_RES_WR_IQPCIECH_M … #define FW_RI_RES_WR_IQPCIECH_V(x) … #define FW_RI_RES_WR_IQPCIECH_G(x) … #define FW_RI_RES_WR_IQDCAEN_S … #define FW_RI_RES_WR_IQDCAEN_M … #define FW_RI_RES_WR_IQDCAEN_V(x) … #define FW_RI_RES_WR_IQDCAEN_G(x) … #define FW_RI_RES_WR_IQDCAEN_F … #define FW_RI_RES_WR_IQDCACPU_S … #define FW_RI_RES_WR_IQDCACPU_M … #define FW_RI_RES_WR_IQDCACPU_V(x) … #define FW_RI_RES_WR_IQDCACPU_G(x) … #define FW_RI_RES_WR_IQINTCNTTHRESH_S … #define FW_RI_RES_WR_IQINTCNTTHRESH_M … #define FW_RI_RES_WR_IQINTCNTTHRESH_V(x) … #define FW_RI_RES_WR_IQINTCNTTHRESH_G(x) … #define FW_RI_RES_WR_IQO_S … #define FW_RI_RES_WR_IQO_M … #define FW_RI_RES_WR_IQO_V(x) … #define FW_RI_RES_WR_IQO_G(x) … #define FW_RI_RES_WR_IQO_F … #define FW_RI_RES_WR_IQCPRIO_S … #define FW_RI_RES_WR_IQCPRIO_M … #define FW_RI_RES_WR_IQCPRIO_V(x) … #define FW_RI_RES_WR_IQCPRIO_G(x) … #define FW_RI_RES_WR_IQCPRIO_F … #define FW_RI_RES_WR_IQESIZE_S … #define FW_RI_RES_WR_IQESIZE_M … #define FW_RI_RES_WR_IQESIZE_V(x) … #define FW_RI_RES_WR_IQESIZE_G(x) … #define FW_RI_RES_WR_IQNS_S … #define FW_RI_RES_WR_IQNS_M … #define FW_RI_RES_WR_IQNS_V(x) … #define FW_RI_RES_WR_IQNS_G(x) … #define FW_RI_RES_WR_IQNS_F … #define FW_RI_RES_WR_IQRO_S … #define FW_RI_RES_WR_IQRO_M … #define FW_RI_RES_WR_IQRO_V(x) … #define FW_RI_RES_WR_IQRO_G(x) … #define FW_RI_RES_WR_IQRO_F … struct fw_ri_rdma_write_wr { … }; struct fw_ri_send_wr { … }; #define FW_RI_SEND_WR_SENDOP_S … #define FW_RI_SEND_WR_SENDOP_M … #define FW_RI_SEND_WR_SENDOP_V(x) … #define FW_RI_SEND_WR_SENDOP_G(x) … struct fw_ri_rdma_write_cmpl_wr { … }; struct fw_ri_rdma_read_wr { … }; struct fw_ri_recv_wr { … }; struct fw_ri_bind_mw_wr { … }; #define FW_RI_BIND_MW_WR_QPBINDE_S … #define FW_RI_BIND_MW_WR_QPBINDE_M … #define FW_RI_BIND_MW_WR_QPBINDE_V(x) … #define FW_RI_BIND_MW_WR_QPBINDE_G(x) … #define FW_RI_BIND_MW_WR_QPBINDE_F … #define FW_RI_BIND_MW_WR_NS_S … #define FW_RI_BIND_MW_WR_NS_M … #define FW_RI_BIND_MW_WR_NS_V(x) … #define FW_RI_BIND_MW_WR_NS_G(x) … #define FW_RI_BIND_MW_WR_NS_F … #define FW_RI_BIND_MW_WR_DCACPU_S … #define FW_RI_BIND_MW_WR_DCACPU_M … #define FW_RI_BIND_MW_WR_DCACPU_V(x) … #define FW_RI_BIND_MW_WR_DCACPU_G(x) … struct fw_ri_fr_nsmr_wr { … }; #define FW_RI_FR_NSMR_WR_QPBINDE_S … #define FW_RI_FR_NSMR_WR_QPBINDE_M … #define FW_RI_FR_NSMR_WR_QPBINDE_V(x) … #define FW_RI_FR_NSMR_WR_QPBINDE_G(x) … #define FW_RI_FR_NSMR_WR_QPBINDE_F … #define FW_RI_FR_NSMR_WR_NS_S … #define FW_RI_FR_NSMR_WR_NS_M … #define FW_RI_FR_NSMR_WR_NS_V(x) … #define FW_RI_FR_NSMR_WR_NS_G(x) … #define FW_RI_FR_NSMR_WR_NS_F … #define FW_RI_FR_NSMR_WR_DCACPU_S … #define FW_RI_FR_NSMR_WR_DCACPU_M … #define FW_RI_FR_NSMR_WR_DCACPU_V(x) … #define FW_RI_FR_NSMR_WR_DCACPU_G(x) … struct fw_ri_fr_nsmr_tpte_wr { … }; struct fw_ri_inv_lstag_wr { … }; enum fw_ri_type { … }; enum fw_ri_init_p2ptype { … }; enum fw_ri_init_rqeqid_srq { … }; struct fw_ri_wr { … }; #define FW_RI_WR_MPAREQBIT_S … #define FW_RI_WR_MPAREQBIT_M … #define FW_RI_WR_MPAREQBIT_V(x) … #define FW_RI_WR_MPAREQBIT_G(x) … #define FW_RI_WR_MPAREQBIT_F … #define FW_RI_WR_P2PTYPE_S … #define FW_RI_WR_P2PTYPE_M … #define FW_RI_WR_P2PTYPE_V(x) … #define FW_RI_WR_P2PTYPE_G(x) … #endif /* _T4FW_RI_API_H_ */
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