/* * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved. * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ /* * This file contains all of the code that is specific to the * InfiniPath 7322 chip */ #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/jiffies.h> #include <linux/module.h> #include <rdma/ib_verbs.h> #include <rdma/ib_smi.h> #ifdef CONFIG_INFINIBAND_QIB_DCA #include <linux/dca.h> #endif #include "qib.h" #include "qib_7322_regs.h" #include "qib_qsfp.h" #include "qib_mad.h" #include "qib_verbs.h" #undef pr_fmt #define pr_fmt(fmt) … static void qib_setup_7322_setextled(struct qib_pportdata *, u32); static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t); static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op); static irqreturn_t qib_7322intr(int irq, void *data); static irqreturn_t qib_7322bufavail(int irq, void *data); static irqreturn_t sdma_intr(int irq, void *data); static irqreturn_t sdma_idle_intr(int irq, void *data); static irqreturn_t sdma_progress_intr(int irq, void *data); static irqreturn_t sdma_cleanup_intr(int irq, void *data); static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32, struct qib_ctxtdata *rcd); static u8 qib_7322_phys_portstate(u64); static u32 qib_7322_iblink_state(u64); static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, u16 linitcmd); static void force_h1(struct qib_pportdata *); static void adj_tx_serdes(struct qib_pportdata *); static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8); static void qib_7322_mini_pcs_reset(struct qib_pportdata *); static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32); static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned); static void serdes_7322_los_enable(struct qib_pportdata *, int); static int serdes_7322_init_old(struct qib_pportdata *); static int serdes_7322_init_new(struct qib_pportdata *); static void dump_sdma_7322_state(struct qib_pportdata *); #define BMASK(msb, lsb) … /* LE2 serdes values for different cases */ #define LE2_DEFAULT … #define LE2_5m … #define LE2_QME … /* Below is special-purpose, so only really works for the IB SerDes blocks. */ #define IBSD(hw_pidx) … /* these are variables for documentation and experimentation purposes */ static const unsigned rcv_int_timeout = …; static const unsigned rcv_int_count = …; static const unsigned sdma_idle_cnt = …; /* Time to stop altering Rx Equalization parameters, after link up. */ #define RXEQ_DISABLE_MSECS … /* * Number of VLs we are configured to use (to allow for more * credits per vl, etc.) */ ushort qib_num_cfg_vls = …; module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO); MODULE_PARM_DESC(…) …; static ushort qib_chase = …; module_param_named(chase, qib_chase, ushort, S_IRUGO); MODULE_PARM_DESC(…) …; static ushort qib_long_atten = …; /* 10 dB ~= 5m length */ module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO); MODULE_PARM_DESC(…) …; static ushort qib_singleport; module_param_named(singleport, qib_singleport, ushort, S_IRUGO); MODULE_PARM_DESC(…) …; static ushort qib_krcvq01_no_msi; module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO); MODULE_PARM_DESC(…) …; /* * Receive header queue sizes */ static unsigned qib_rcvhdrcnt; module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO); MODULE_PARM_DESC(…) …; static unsigned qib_rcvhdrsize; module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO); MODULE_PARM_DESC(…) …; static unsigned qib_rcvhdrentsize; module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO); MODULE_PARM_DESC(…) …; #define MAX_ATTEN_LEN … /* for read back, default index is ~5m copper cable */ static char txselect_list[MAX_ATTEN_LEN] = …; static struct kparam_string kp_txselect = …; static int setup_txselect(const char *, const struct kernel_param *); module_param_call(…); MODULE_PARM_DESC(…) …; #define BOARD_QME7342 … #define BOARD_QMH7342 … #define BOARD_QMH7360 … #define IS_QMH(dd) … #define IS_QME(dd) … #define KREG_IDX(regname) … #define KREG_IBPORT_IDX(regname) … #define MASK_ACROSS(lsb, msb) … #define SYM_RMASK(regname, fldname) … #define SYM_MASK(regname, fldname) … #define SYM_FIELD(value, regname, fldname) … /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */ #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) … #define HWE_MASK(fldname) … #define ERR_MASK(fldname) … #define ERR_MASK_N(fldname) … #define INT_MASK(fldname) … #define INT_MASK_P(fldname, port) … /* Below because most, but not all, fields of IntMask have that full suffix */ #define INT_MASK_PM(fldname, port) … #define SYM_LSB(regname, fldname) … /* * the size bits give us 2^N, in KB units. 0 marks as invalid, * and 7 is reserved. We currently use only 2KB and 4KB */ #define IBA7322_TID_SZ_SHIFT … #define IBA7322_TID_SZ_2K … #define IBA7322_TID_SZ_4K … #define IBA7322_TID_PA_SHIFT … #define SendIBSLIDAssignMask … #define SendIBSLMCMask … #define ExtLED_IB1_YEL … #define ExtLED_IB1_GRN … #define ExtLED_IB2_YEL … #define ExtLED_IB2_GRN … #define ExtLED_IB1_MASK … #define ExtLED_IB2_MASK … #define _QIB_GPIO_SDA_NUM … #define _QIB_GPIO_SCL_NUM … #define QIB_EEPROM_WEN_NUM … #define QIB_TWSI_EEPROM_DEV … /* HW counter clock is at 4nsec */ #define QIB_7322_PSXMITWAIT_CHECK_RATE … /* full speed IB port 1 only */ #define PORT_SPD_CAP … #define PORT_SPD_CAP_SHIFT … /* full speed featuremask, both ports */ #define DUAL_PORT_CAP … /* * This file contains almost all the chip-specific register information and * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip. */ /* Use defines to tie machine-generated names to lower-case names */ #define kr_contextcnt … #define kr_control … #define kr_counterregbase … #define kr_errclear … #define kr_errmask … #define kr_errstatus … #define kr_extctrl … #define kr_extstatus … #define kr_gpio_clear … #define kr_gpio_mask … #define kr_gpio_out … #define kr_gpio_status … #define kr_hwdiagctrl … #define kr_debugportval … #define kr_fmask … #define kr_act_fmask … #define kr_hwerrclear … #define kr_hwerrmask … #define kr_hwerrstatus … #define kr_intclear … #define kr_intmask … #define kr_intredirect … #define kr_intstatus … #define kr_pagealign … #define kr_rcvavailtimeout … #define kr_rcvctrl … #define kr_rcvegrbase … #define kr_rcvegrcnt … #define kr_rcvhdrcnt … #define kr_rcvhdrentsize … #define kr_rcvhdrsize … #define kr_rcvtidbase … #define kr_rcvtidcnt … #define kr_revision … #define kr_scratch … #define kr_sendbuffererror … #define kr_sendcheckmask … #define kr_sendctrl … #define kr_sendgrhcheckmask … #define kr_sendibpktmask … #define kr_sendpioavailaddr … #define kr_sendpiobufbase … #define kr_sendpiobufcnt … #define kr_sendpiosize … #define kr_sendregbase … #define kr_sendbufavail0 … #define kr_userregbase … #define kr_intgranted … #define kr_vecclr_wo_int … #define kr_intblocked … #define kr_r_access … /* * per-port kernel registers. Access only with qib_read_kreg_port() * or qib_write_kreg_port() */ #define krp_errclear … #define krp_errmask … #define krp_errstatus … #define krp_highprio_0 … #define krp_highprio_limit … #define krp_hrtbt_guid … #define krp_ib_pcsconfig … #define krp_ibcctrl_a … #define krp_ibcctrl_b … #define krp_ibcctrl_c … #define krp_ibcstatus_a … #define krp_ibcstatus_b … #define krp_txestatus … #define krp_lowprio_0 … #define krp_ncmodectrl … #define krp_partitionkey … #define krp_psinterval … #define krp_psstart … #define krp_psstat … #define krp_rcvbthqp … #define krp_rcvctrl … #define krp_rcvpktledcnt … #define krp_rcvqpmaptable … #define krp_rxcreditvl0 … #define krp_rxcreditvl15 … #define krp_sendcheckcontrol … #define krp_sendctrl … #define krp_senddmabase … #define krp_senddmabufmask0 … #define krp_senddmabufmask1 … #define krp_senddmabufmask2 … #define krp_senddmabuf_use0 … #define krp_senddmabuf_use1 … #define krp_senddmabuf_use2 … #define krp_senddmadesccnt … #define krp_senddmahead … #define krp_senddmaheadaddr … #define krp_senddmaidlecnt … #define krp_senddmalengen … #define krp_senddmaprioritythld … #define krp_senddmareloadcnt … #define krp_senddmastatus … #define krp_senddmatail … #define krp_sendhdrsymptom … #define krp_sendslid … #define krp_sendslidmask … #define krp_ibsdtestiftx … #define krp_adapt_dis_timer … #define krp_tx_deemph_override … #define krp_serdesctrl … /* * Per-context kernel registers. Access only with qib_read_kreg_ctxt() * or qib_write_kreg_ctxt() */ #define krc_rcvhdraddr … #define krc_rcvhdrtailaddr … /* * TID Flow table, per context. Reduces * number of hdrq updates to one per flow (or on errors). * context 0 and 1 share same memory, but have distinct * addresses. Since for now, we never use expected sends * on kernel contexts, we don't worry about that (we initialize * those entries for ctxt 0/1 on driver load twice, for example). */ #define NUM_TIDFLOWS_CTXT … #define ur_rcvflowtable … /* these are the error bits in the tid flows, and are W1C */ #define TIDFLOW_ERRBITS … /* Most (not all) Counters are per-IBport. * Requires LBIntCnt is at offset 0 in the group */ #define CREG_IDX(regname) … #define crp_badformat … #define crp_err_rlen … #define crp_erricrc … #define crp_errlink … #define crp_errlpcrc … #define crp_errpkey … #define crp_errvcrc … #define crp_excessbufferovfl … #define crp_iblinkdown … #define crp_iblinkerrrecov … #define crp_ibstatuschange … #define crp_ibsymbolerr … #define crp_invalidrlen … #define crp_locallinkintegrityerr … #define crp_pktrcv … #define crp_pktrcvflowctrl … #define crp_pktsend … #define crp_pktsendflow … #define crp_psrcvdatacount … #define crp_psrcvpktscount … #define crp_psxmitdatacount … #define crp_psxmitpktscount … #define crp_psxmitwaitcount … #define crp_rcvebp … #define crp_rcvflowctrlviol … #define crp_rcvovfl … #define crp_rxdlidfltr … #define crp_rxdroppkt … #define crp_rxotherlocalphyerr … #define crp_rxqpinvalidctxt … #define crp_rxvlerr … #define crp_sendstall … #define crp_txdroppedpkt … #define crp_txhdrerr … #define crp_txlenerr … #define crp_txminmaxlenerr … #define crp_txsdmadesc … #define crp_txunderrun … #define crp_txunsupvl … #define crp_vl15droppedpkt … #define crp_wordrcv … #define crp_wordsend … #define crp_tx_creditstalls … /* these are the (few) counters that are not port-specific */ #define CREG_DEVIDX(regname) … #define cr_base_egrovfl … #define cr_lbint … #define cr_lbstall … #define cr_pcieretrydiag … #define cr_rxtidflowdrop … #define cr_tidfull … #define cr_tidinvalid … /* no chip register for # of IB ports supported, so define */ #define NUM_IB_PORTS … /* 1 VL15 buffer per hardware IB port, no register for this, so define */ #define NUM_VL15_BUFS … /* * context 0 and 1 are special, and there is no chip register that * defines this value, so we have to define it here. * These are all allocated to either 0 or 1 for single port * hardware configuration, otherwise each gets half */ #define KCTXT0_EGRCNT … /* values for vl and port fields in PBC, 7322-specific */ #define PBC_PORT_SEL_LSB … #define PBC_PORT_SEL_RMASK … #define PBC_VL_NUM_LSB … #define PBC_VL_NUM_RMASK … #define PBC_7322_VL15_SEND … #define PBC_7322_VL15_SEND_CTRL … static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = …; static const char * const qib_sdma_state_names[] = …; #define IBA7322_LINKSPEED_SHIFT … #define IBA7322_LINKWIDTH_SHIFT … /* link training states, from IBC */ #define IB_7322_LT_STATE_DISABLED … #define IB_7322_LT_STATE_LINKUP … #define IB_7322_LT_STATE_POLLACTIVE … #define IB_7322_LT_STATE_POLLQUIET … #define IB_7322_LT_STATE_SLEEPDELAY … #define IB_7322_LT_STATE_SLEEPQUIET … #define IB_7322_LT_STATE_CFGDEBOUNCE … #define IB_7322_LT_STATE_CFGRCVFCFG … #define IB_7322_LT_STATE_CFGWAITRMT … #define IB_7322_LT_STATE_CFGIDLE … #define IB_7322_LT_STATE_RECOVERRETRAIN … #define IB_7322_LT_STATE_TXREVLANES … #define IB_7322_LT_STATE_RECOVERWAITRMT … #define IB_7322_LT_STATE_RECOVERIDLE … #define IB_7322_LT_STATE_CFGENH … #define IB_7322_LT_STATE_CFGTEST … #define IB_7322_LT_STATE_CFGWAITRMTTEST … #define IB_7322_LT_STATE_CFGWAITENH … /* link state machine states from IBC */ #define IB_7322_L_STATE_DOWN … #define IB_7322_L_STATE_INIT … #define IB_7322_L_STATE_ARM … #define IB_7322_L_STATE_ACTIVE … #define IB_7322_L_STATE_ACT_DEFER … static const u8 qib_7322_physportstate[0x20] = …; #ifdef CONFIG_INFINIBAND_QIB_DCA struct qib_irq_notify { … }; #endif struct qib_chip_specific { … }; /* Table of entries in "human readable" form Tx Emphasis. */ struct txdds_ent { … }; struct vendor_txdds_ent { … }; static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *); #define TXDDS_TABLE_SZ … #define TXDDS_EXTRA_SZ … #define TXDDS_MFG_SZ … #define SERDES_CHANS … #define H1_FORCE_VAL … #define H1_FORCE_QME … #define H1_FORCE_QMH … /* The static and dynamic registers are paired, and the pairs indexed by spd */ #define krp_static_adapt_dis(spd) … #define QDR_DFE_DISABLE_DELAY … #define QDR_STATIC_ADAPT_DOWN … #define QDR_STATIC_ADAPT_DOWN_R1 … #define QDR_STATIC_ADAPT_INIT … #define QDR_STATIC_ADAPT_INIT_R1 … struct qib_chippport_specific { … }; static struct { … } irq_table[] = …; #ifdef CONFIG_INFINIBAND_QIB_DCA static const struct dca_reg_map { … } dca_rcvhdr_reg_map[] = …; #endif /* ibcctrl bits */ #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE … /* cycle through TS1/TS2 till OK */ #define QLOGIC_IB_IBCC_LINKINITCMD_POLL … /* wait for TS1, then go on */ #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP … #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT … #define QLOGIC_IB_IBCC_LINKCMD_DOWN … #define QLOGIC_IB_IBCC_LINKCMD_ARMED … #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE … #define BLOB_7322_IBCHG … static inline void qib_write_kreg(const struct qib_devdata *dd, const u32 regno, u64 value); static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32); static void write_7322_initregs(struct qib_devdata *); static void write_7322_init_portregs(struct qib_pportdata *); static void setup_7322_link_recovery(struct qib_pportdata *, u32); static void check_7322_rxe_status(struct qib_pportdata *); static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *); #ifdef CONFIG_INFINIBAND_QIB_DCA static void qib_setup_dca(struct qib_devdata *dd); static void setup_dca_notifier(struct qib_devdata *dd, int msixnum); static void reset_dca_notifier(struct qib_devdata *dd, int msixnum); #endif /** * qib_read_ureg32 - read 32-bit virtualized per-context register * @dd: device * @regno: register number * @ctxt: context number * * Return the contents of a register that is virtualized to be per context. * Returns -1 on errors (not distinguishable from valid contents at * runtime; we may add a separate error variable at some point). */ static inline u32 qib_read_ureg32(const struct qib_devdata *dd, enum qib_ureg regno, int ctxt) { … } /** * qib_write_ureg - write virtualized per-context register * @dd: device * @regno: register number * @value: value * @ctxt: context * * Write the contents of a register that is virtualized to be per context. */ static inline void qib_write_ureg(const struct qib_devdata *dd, enum qib_ureg regno, u64 value, int ctxt) { … } static inline u32 qib_read_kreg32(const struct qib_devdata *dd, const u32 regno) { … } static inline u64 qib_read_kreg64(const struct qib_devdata *dd, const u32 regno) { … } static inline void qib_write_kreg(const struct qib_devdata *dd, const u32 regno, u64 value) { … } /* * not many sanity checks for the port-specific kernel register routines, * since they are only used when it's known to be safe. */ static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd, const u16 regno) { … } static inline void qib_write_kreg_port(const struct qib_pportdata *ppd, const u16 regno, u64 value) { … } /** * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register * @dd: the qlogic_ib device * @regno: the register number to write * @ctxt: the context containing the register * @value: the value to write */ static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, const u16 regno, unsigned ctxt, u64 value) { … } static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno) { … } static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno) { … } static inline void write_7322_creg_port(const struct qib_pportdata *ppd, u16 regno, u64 value) { … } static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd, u16 regno) { … } static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd, u16 regno) { … } /* bits in Control register */ #define QLOGIC_IB_C_RESET … #define QLOGIC_IB_C_SDMAFETCHPRIOEN … /* bits in general interrupt regs */ #define QIB_I_RCVURG_LSB … #define QIB_I_RCVURG_RMASK … #define QIB_I_RCVURG_MASK … #define QIB_I_RCVAVAIL_LSB … #define QIB_I_RCVAVAIL_RMASK … #define QIB_I_RCVAVAIL_MASK … #define QIB_I_C_ERROR … #define QIB_I_SPIOSENT … #define QIB_I_SPIOBUFAVAIL … #define QIB_I_GPIO … #define QIB_I_P_SDMAINT(pidx) … /* Interrupt bits that are "per port" */ #define QIB_I_P_BITSEXTANT(pidx) … /* Interrupt bits that are common to a device */ /* currently unused: QIB_I_SPIOSENT */ #define QIB_I_C_BITSEXTANT … #define QIB_I_BITSEXTANT … /* * Error bits that are "per port". */ #define QIB_E_P_IBSTATUSCHANGED … #define QIB_E_P_SHDR … #define QIB_E_P_VL15_BUF_MISUSE … #define QIB_E_P_SND_BUF_MISUSE … #define QIB_E_P_SUNSUPVL … #define QIB_E_P_SUNEXP_PKTNUM … #define QIB_E_P_SDROP_DATA … #define QIB_E_P_SDROP_SMP … #define QIB_E_P_SPKTLEN … #define QIB_E_P_SUNDERRUN … #define QIB_E_P_SMAXPKTLEN … #define QIB_E_P_SMINPKTLEN … #define QIB_E_P_RIBLOSTLINK … #define QIB_E_P_RHDR … #define QIB_E_P_RHDRLEN … #define QIB_E_P_RBADTID … #define QIB_E_P_RBADVERSION … #define QIB_E_P_RIBFLOW … #define QIB_E_P_REBP … #define QIB_E_P_RUNSUPVL … #define QIB_E_P_RUNEXPCHAR … #define QIB_E_P_RSHORTPKTLEN … #define QIB_E_P_RLONGPKTLEN … #define QIB_E_P_RMAXPKTLEN … #define QIB_E_P_RMINPKTLEN … #define QIB_E_P_RICRC … #define QIB_E_P_RVCRC … #define QIB_E_P_RFORMATERR … #define QIB_E_P_SDMA1STDESC … #define QIB_E_P_SDMABASE … #define QIB_E_P_SDMADESCADDRMISALIGN … #define QIB_E_P_SDMADWEN … #define QIB_E_P_SDMAGENMISMATCH … #define QIB_E_P_SDMAHALT … #define QIB_E_P_SDMAMISSINGDW … #define QIB_E_P_SDMAOUTOFBOUND … #define QIB_E_P_SDMARPYTAG … #define QIB_E_P_SDMATAILOUTOFBOUND … #define QIB_E_P_SDMAUNEXPDATA … /* Error bits that are common to a device */ #define QIB_E_RESET … #define QIB_E_HARDWARE … #define QIB_E_INVALIDADDR … /* * Per chip (rather than per-port) errors. Most either do * nothing but trigger a print (because they self-recover, or * always occur in tandem with other errors that handle the * issue), or because they indicate errors with no recovery, * but we want to know that they happened. */ #define QIB_E_SBUF_VL15_MISUSE … #define QIB_E_BADEEP … #define QIB_E_VLMISMATCH … #define QIB_E_ARMLAUNCH … #define QIB_E_SPCLTRIG … #define QIB_E_RRCVHDRFULL … #define QIB_E_RRCVEGRFULL … #define QIB_E_RCVCTXTSHARE … /* SDMA chip errors (not per port) * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get * the SDMAHALT error immediately, so we just print the dup error via the * E_AUTO mechanism. This is true of most of the per-port fatal errors * as well, but since this is port-independent, by definition, it's * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per * packet send errors, and so are handled in the same manner as other * per-packet errors. */ #define QIB_E_SDMA_VL15 … #define QIB_E_SDMA_WRONG_PORT … #define QIB_E_SDMA_BUF_DUP … /* * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS * it is used to print "common" packet errors. */ #define QIB_E_P_PKTERRS … /* Error Bits that Packet-related (Receive, per-port) */ #define QIB_E_P_RPKTERRS … /* * Error bits that are Send-related (per port) * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling). * All of these potentially need to have a buffer disarmed */ #define QIB_E_P_SPKTERRS … #define QIB_E_SPKTERRS … #define QIB_E_P_SDMAERRS … /* * This sets some bits more than once, but makes it more obvious which * bits are not handled under other categories, and the repeat definition * is not a problem. */ #define QIB_E_P_BITSEXTANT … /* * These are errors that can occur when the link * changes state while a packet is being sent or received. This doesn't * cover things like EBP or VCRC that can be the result of a sending * having the link change state, so we receive a "known bad" packet. * All of these are "per port", so renamed: */ #define QIB_E_P_LINK_PKTERRS … /* * This sets some bits more than once, but makes it more obvious which * bits are not handled under other categories (such as QIB_E_SPKTERRS), * and the repeat definition is not a problem. */ #define QIB_E_C_BITSEXTANT … /* Likewise Neuter E_SPKT_ERRS_IGNORE */ #define E_SPKT_ERRS_IGNORE … #define QIB_EXTS_MEMBIST_DISABLED … #define QIB_EXTS_MEMBIST_ENDTEST … #define QIB_E_SPIOARMLAUNCH … #define IBA7322_IBCC_LINKINITCMD_MASK … #define IBA7322_IBCC_LINKCMD_SHIFT … /* * IBTA_1_2 is set when multiple speeds are enabled (normal), * and also if forced QDR (only QDR enabled). It's enabled for the * forced QDR case so that scrambling will be enabled by the TS3 * exchange, when supported by both sides of the link. */ #define IBA7322_IBC_IBTA_1_2_MASK … #define IBA7322_IBC_MAX_SPEED_MASK … #define IBA7322_IBC_SPEED_QDR … #define IBA7322_IBC_SPEED_DDR … #define IBA7322_IBC_SPEED_SDR … #define IBA7322_IBC_SPEED_MASK … #define IBA7322_IBC_SPEED_LSB … #define IBA7322_LEDBLINK_OFF_SHIFT … #define IBA7322_LEDBLINK_ON_SHIFT … #define IBA7322_IBC_WIDTH_AUTONEG … #define IBA7322_IBC_WIDTH_4X_ONLY … #define IBA7322_IBC_WIDTH_1X_ONLY … #define IBA7322_IBC_RXPOL_MASK … #define IBA7322_IBC_RXPOL_LSB … #define IBA7322_IBC_HRTBT_MASK … #define IBA7322_IBC_HRTBT_RMASK … #define IBA7322_IBC_HRTBT_LSB … #define IBA7322_REDIRECT_VEC_PER_REG … #define IBA7322_SENDCHK_PKEY … #define IBA7322_SENDCHK_BTHQP … #define IBA7322_SENDCHK_SLID … #define IBA7322_SENDCHK_RAW_IPV6 … #define IBA7322_SENDCHK_MINSZ … #define AUTONEG_TRIES … #define HWE_AUTO(fldname) … #define HWE_AUTO_P(fldname, port) … static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = …; #define E_AUTO(fldname) … #define E_P_AUTO(fldname) … static const struct qib_hwerror_msgs qib_7322error_msgs[] = …; static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = …; /* * Below generates "auto-message" for interrupts not specific to any port or * context */ #define INTR_AUTO(fldname) … /* Below generates "auto-message" for interrupts specific to a port */ #define INTR_AUTO_P(fldname) … /* For some reason, the SerDesTrimDone bits are reversed */ #define INTR_AUTO_PI(fldname) … /* * Below generates "auto-message" for interrupts specific to a context, * with ctxt-number appended */ #define INTR_AUTO_C(fldname) … #define TXSYMPTOM_AUTO_P(fldname) … static const struct qib_hwerror_msgs hdrchk_msgs[] = …; #define IBA7322_HDRHEAD_PKTINT_SHIFT … /* * Called when we might have an error that is specific to a particular * PIO buffer, and may need to cancel that buffer, so it can be re-used, * because we don't need to force the update of pioavail */ static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd) { … } /* No txe_recover yet, if ever */ /* No decode__errors yet */ static void err_decode(char *msg, size_t len, u64 errs, const struct qib_hwerror_msgs *msp) { … } /* only called if r1 set */ static void flush_fifo(struct qib_pportdata *ppd) { … } /* * This is called with interrupts disabled and sdma_lock held. */ static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op) { … } static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd) { … } static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd) { … } /* * Must be called with sdma_lock held, or before init finished. */ static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail) { … } /* * This is called with interrupts disabled and sdma_lock held. */ static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd) { … } #define DISABLES_SDMA … static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs) { … } /* * handle per-device errors (not per-port errors) */ static noinline void handle_7322_errors(struct qib_devdata *dd) { … } static void qib_error_tasklet(struct tasklet_struct *t) { … } static void reenable_chase(struct timer_list *t) { … } static void disable_chase(struct qib_pportdata *ppd, unsigned long tnow, u8 ibclt) { … } static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst) { … } static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32); /* * This is per-pport error handling. * will likely get it's own MSIx interrupt (one for each port, * although just a single handler). */ static noinline void handle_7322_p_errors(struct qib_pportdata *ppd) { … } /* enable/disable chip from delivering interrupts */ static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable) { … } /* * Try to cleanup as much as possible for anything that might have gone * wrong while in freeze mode, such as pio buffers being written by user * processes (causing armlaunch), send errors due to going into freeze mode, * etc., and try to avoid causing extra interrupts while doing so. * Forcibly update the in-memory pioavail register copies after cleanup * because the chip won't do it while in freeze mode (the register values * themselves are kept correct). * Make sure that we don't lose any important interrupts by using the chip * feature that says that writing 0 to a bit in *clear that is set in * *status will cause an interrupt to be generated again (if allowed by * the *mask value). * This is in chip-specific code because of all of the register accesses, * even though the details are similar on most chips. */ static void qib_7322_clear_freeze(struct qib_devdata *dd) { … } /* no error handling to speak of */ /** * qib_7322_handle_hwerrors - display hardware errors. * @dd: the qlogic_ib device * @msg: the output buffer * @msgl: the size of the output buffer * * Use same msg buffer as regular errors to avoid excessive stack * use. Most hardware errors are catastrophic, but for right now, * we'll print them and continue. We reuse the same message buffer as * qib_handle_errors() to avoid excessive stack usage. */ static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg, size_t msgl) { … } /** * qib_7322_init_hwerrors - enable hardware errors * @dd: the qlogic_ib device * * now that we have finished initializing everything that might reasonably * cause a hardware error, and cleared those errors bits as they occur, * we can enable hardware errors in the mask (potentially enabling * freeze mode), and enable hardware errors as errors (along with * everything else) in errormask */ static void qib_7322_init_hwerrors(struct qib_devdata *dd) { … } /* * Disable and enable the armlaunch error. Used for PIO bandwidth testing * on chips that are count-based, rather than trigger-based. There is no * reference counting, but that's also fine, given the intended use. * Only chip-specific because it's all register accesses */ static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable) { … } /* * Formerly took parameter <which> in pre-shifted, * pre-merged form with LinkCmd and LinkInitCmd * together, and assuming the zero was NOP. */ static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd, u16 linitcmd) { … } /* * The total RCV buffer memory is 64KB, used for both ports, and is * in units of 64 bytes (same as IB flow control credit unit). * The consumedVL unit in the same registers are in 32 byte units! * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks, * and we can therefore allocate just 9 IB credits for 2 VL15 packets * in krp_rxcreditvl15, rather than 10. */ #define RCV_BUF_UNITSZ … #define NUM_RCV_BUF_UNITS(dd) … static void set_vls(struct qib_pportdata *ppd) { … } /* * The code that deals with actual SerDes is in serdes_7322_init(). * Compared to the code for iba7220, it is minimal. */ static int serdes_7322_init(struct qib_pportdata *ppd); /** * qib_7322_bringup_serdes - bring up the serdes * @ppd: physical port on the qlogic_ib device */ static int qib_7322_bringup_serdes(struct qib_pportdata *ppd) { … } /** * qib_7322_mini_quiet_serdes - set serdes to txidle * @ppd: the qlogic_ib device * Called when driver is being unloaded */ static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd) { … } /** * qib_setup_7322_setextled - set the state of the two external LEDs * @ppd: physical port on the qlogic_ib device * @on: whether the link is up or not * * The exact combo of LEDs if on is true is determined by looking * at the ibcstatus. * * These LEDs indicate the physical and logical state of IB link. * For this chip (at least with recommended board pinouts), LED1 * is Yellow (logical state) and LED2 is Green (physical state), * * Note: We try to match the Mellanox HCA LED behavior as best * we can. Green indicates physical link state is OK (something is * plugged in, and we can train). * Amber indicates the link is logically up (ACTIVE). * Mellanox further blinks the amber LED to indicate data packet * activity, but we have no hardware support for that, so it would * require waking up every 10-20 msecs and checking the counters * on the chip, and then turning the LED off if appropriate. That's * visible overhead, so not something we will do. */ static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on) { … } #ifdef CONFIG_INFINIBAND_QIB_DCA static int qib_7322_notify_dca(struct qib_devdata *dd, unsigned long event) { … } static void qib_update_rhdrq_dca(struct qib_ctxtdata *rcd, int cpu) { … } static void qib_update_sdma_dca(struct qib_pportdata *ppd, int cpu) { … } static void qib_setup_dca(struct qib_devdata *dd) { … } static void qib_irq_notifier_notify(struct irq_affinity_notify *notify, const cpumask_t *mask) { … } static void qib_irq_notifier_release(struct kref *ref) { … } #endif static void qib_7322_free_irq(struct qib_devdata *dd) { … } static void qib_setup_7322_cleanup(struct qib_devdata *dd) { … } /* handle SDMA interrupts */ static void sdma_7322_intr(struct qib_devdata *dd, u64 istat) { … } /* * Set or clear the Send buffer available interrupt enable bit. */ static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint) { … } /* * Somehow got an interrupt with reserved bits set in interrupt status. * Print a message so we know it happened, then clear them. * keep mainline interrupt handler cache-friendly */ static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat) { … } /* keep mainline interrupt handler cache-friendly */ static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd) { … } /* * Handle errors and unusual events first, separate function * to improve cache hits for fast path interrupt handling. */ static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat) { … } /* * Dynamically adjust the rcv int timeout for a context based on incoming * packet rate. */ static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts) { … } /* * This is the main interrupt handler. * It will normally only be used for low frequency interrupts but may * have to handle all interrupts if INTx is enabled or fewer than normal * MSIx interrupts were allocated. * This routine should ignore the interrupt bits for any of the * dedicated MSIx handlers. */ static irqreturn_t qib_7322intr(int irq, void *data) { … } /* * Dedicated receive packet available interrupt handler. */ static irqreturn_t qib_7322pintr(int irq, void *data) { … } /* * Dedicated Send buffer available interrupt handler. */ static irqreturn_t qib_7322bufavail(int irq, void *data) { … } /* * Dedicated Send DMA interrupt handler. */ static irqreturn_t sdma_intr(int irq, void *data) { … } /* * Dedicated Send DMA idle interrupt handler. */ static irqreturn_t sdma_idle_intr(int irq, void *data) { … } /* * Dedicated Send DMA progress interrupt handler. */ static irqreturn_t sdma_progress_intr(int irq, void *data) { … } /* * Dedicated Send DMA cleanup interrupt handler. */ static irqreturn_t sdma_cleanup_intr(int irq, void *data) { … } #ifdef CONFIG_INFINIBAND_QIB_DCA static void reset_dca_notifier(struct qib_devdata *dd, int msixnum) { … } static void setup_dca_notifier(struct qib_devdata *dd, int msixnum) { … } #endif /* * Set up our chip-specific interrupt handler. * The interrupt type has already been setup, so * we just need to do the registration and error checking. * If we are using MSIx interrupts, we may fall back to * INTx later, if the interrupt handler doesn't get called * within 1/2 second (see verify_interrupt()). */ static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend) { … } /** * qib_7322_boardname - fill in the board name and note features * @dd: the qlogic_ib device * * info will be based on the board revision register */ static unsigned qib_7322_boardname(struct qib_devdata *dd) { … } /* * This routine sleeps, so it can only be called from user context, not * from interrupt context. */ static int qib_do_7322_reset(struct qib_devdata *dd) { … } /** * qib_7322_put_tid - write a TID to the chip * @dd: the qlogic_ib device * @tidptr: pointer to the expected TID (in chip) to update * @type: 0 for eager, 1 for expected * @pa: physical address of in memory buffer; tidinvalid if freeing */ static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, u32 type, unsigned long pa) { … } /** * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager * @dd: the qlogic_ib device * @rcd: the ctxt * * clear all TID entries for a ctxt, expected and eager. * Used from qib_close(). */ static void qib_7322_clear_tids(struct qib_devdata *dd, struct qib_ctxtdata *rcd) { … } /** * qib_7322_tidtemplate - setup constants for TID updates * @dd: the qlogic_ib device * * We setup stuff that we use a lot, to avoid calculating each time */ static void qib_7322_tidtemplate(struct qib_devdata *dd) { … } /** * qib_7322_get_base_info - set chip-specific flags for user code * @rcd: the qlogic_ib ctxt * @kinfo: qib_base_info pointer * * We set the PCIE flag because the lower bandwidth on PCIe vs * HyperTransport can affect some user packet algorithims. */ static int qib_7322_get_base_info(struct qib_ctxtdata *rcd, struct qib_base_info *kinfo) { … } static struct qib_message_header * qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) { … } /* * Configure number of contexts. */ static void qib_7322_config_ctxts(struct qib_devdata *dd) { … } static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which) { … } /* * Below again cribbed liberally from older version. Do not lean * heavily on it. */ #define IBA7322_IBC_DLIDLMC_SHIFT … #define IBA7322_IBC_DLIDLMC_MASK … static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val) { … } static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what) { … } static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno, struct ib_vl_weight_elem *vl) { … } static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno, struct ib_vl_weight_elem *vl) { … } static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t) { … } static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t) { … } static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd, u32 updegr, u32 egrhd, u32 npkts) { … } static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd) { … } #define RCVCTRL_COMMON_MODS … #define RCVCTRL_PORT_MODS … /* * Modify the RCVCTRL register in chip-specific way. This * is a function because bit positions and (future) register * location is chip-specifc, but the needed operations are * generic. <op> is a bit-mask because we often want to * do multiple modifications. */ static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op, int ctxt) { … } /* * Modify the SENDCTRL register in chip-specific way. This * is a function where there are multiple such registers with * slightly different layouts. * The chip doesn't allow back-to-back sendctrl writes, so write * the scratch register after writing sendctrl. * * Which register is written depends on the operation. * Most operate on the common register, while * SEND_ENB and SEND_DIS operate on the per-port ones. * SEND_ENB is included in common because it can change SPCL_TRIG */ #define SENDCTRL_COMMON_MODS … #define SENDCTRL_PORT_MODS … static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op) { … } #define _PORT_VIRT_FLAG … #define _PORT_64BIT_FLAG … #define _PORT_CNTR_IDXMASK … /** * qib_portcntr_7322 - read a per-port chip counter * @ppd: the qlogic_ib pport * @reg: the counter to read (not a chip offset) */ static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg) { … } /* * Device counter names (not port-specific), one line per stat, * single string. Used by utilities like ipathstats to print the stats * in a way which works for different versions of drivers, without changing * the utility. Names need to be 12 chars or less (w/o newline), for proper * display by utility. * Non-error counters are first. * Start of "error" conters is indicated by a leading "E " on the first * "error" counter, and doesn't count in label length. * The EgrOvfl list needs to be last so we truncate them at the configured * context count for the device. * cntr7322indices contains the corresponding register indices. */ static const char cntr7322names[] = … ; static const u32 cntr7322indices[] = …; /* * same as cntr7322names and cntr7322indices, but for port-specific counters. * portcntr7322indices is somewhat complicated by some registers needing * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG */ static const char portcntr7322names[] = … ; static const u32 portcntr7322indices[] = …; /* do all the setup to make the counter reads efficient later */ static void init_7322_cntrnames(struct qib_devdata *dd) { … } static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep, u64 **cntrp) { … } static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, char **namep, u64 **cntrp) { … } /** * qib_get_7322_faststats - get word counters from chip before they overflow * @t: contains a pointer to the qlogic_ib device qib_devdata * * VESTIGIAL IBA7322 has no "small fast counters", so the only * real purpose of this function is to maintain the notion of * "active time", which in turn is only logged into the eeprom, * which we don;t have, yet, for 7322-based boards. * * called from add_timer */ static void qib_get_7322_faststats(struct timer_list *t) { … } /* * If we were using MSIx, try to fallback to INTx. */ static int qib_7322_intr_fallback(struct qib_devdata *dd) { … } /* * Reset the XGXS (between serdes and IBC). Slightly less intrusive * than resetting the IBC or external link state, and useful in some * cases to cause some retraining. To do this right, we reset IBC * as well, then return to previous state (which may be still in reset) * NOTE: some callers of this "know" this writes the current value * of cpspec->ibcctrl_a as part of it's operation, so if that changes, * check all callers. */ static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd) { … } /* * This code for non-IBTA-compliant IB speed negotiation is only known to * work for the SDR to DDR transition, and only between an HCA and a switch * with recent firmware. It is based on observed heuristics, rather than * actual knowledge of the non-compliant speed negotiation. * It has a number of hard-coded fields, since the hope is to rewrite this * when a spec is available on how the negoation is intended to work. */ static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr, u32 dcnt, u32 *data) { … } /* * _start packet gets sent twice at start, _done gets sent twice at end */ static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which) { … } /* * Do the absolute minimum to cause an IB speed change, and make it * ready, but don't actually trigger the change. The caller will * do that when ready (if link is in Polling training state, it will * happen immediately, otherwise when link next goes down) * * This routine should only be used as part of the DDR autonegotation * code for devices that are not compliant with IB 1.2 (or code that * fixes things up for same). * * When link has gone down, and autoneg enabled, or autoneg has * failed and we give up until next time we set both speeds, and * then we want IBTA enabled as well as "use max enabled speed. */ static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed) { … } /* * This routine is only used when we are not talking to another * IB 1.2-compliant device that we think can do DDR. * (This includes all existing switch chips as of Oct 2007.) * 1.2-compliant devices go directly to DDR prior to reaching INIT */ static void try_7322_autoneg(struct qib_pportdata *ppd) { … } /* * Handle the empirically determined mechanism for auto-negotiation * of DDR speed with switches. */ static void autoneg_7322_work(struct work_struct *work) { … } /* * This routine is used to request IPG set in the QLogic switch. * Only called if r1. */ static void try_7322_ipg(struct qib_pportdata *ppd) { … } /* * Timeout handler for setting IPG. * Only called if r1. */ static void ipg_7322_work(struct work_struct *work) { … } static u32 qib_7322_iblink_state(u64 ibcs) { … } /* returns the IBTA port state, rather than the IBC link training state */ static u8 qib_7322_phys_portstate(u64 ibcs) { … } static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs) { … } /* * Does read/modify/write to appropriate registers to * set output and direction bits selected by mask. * these are in their canonical positions (e.g. lsb of * dir will end up in D48 of extctrl on existing chips). * returns contents of GP Inputs. */ static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) { … } /* Enable writes to config EEPROM, if possible. Returns previous state */ static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen) { … } /* * Read fundamental info we need to use the chip. These are * the registers that describe chip capabilities, and are * saved in shadow registers. */ static void get_7322_chip_params(struct qib_devdata *dd) { … } /* * The chip base addresses in cspec and cpspec have to be set * after possible init_chip_wc_pat(), rather than in * get_7322_chip_params(), so split out as separate function */ static void qib_7322_set_baseaddrs(struct qib_devdata *dd) { … } /* * This is a fairly special-purpose observer, so we only support * the port-specific parts of SendCtrl */ #define SENDCTRL_SHADOWED … static int sendctrl_hook(struct qib_devdata *dd, const struct diag_observer *op, u32 offs, u64 *data, u64 mask, int only_32) { … } static const struct diag_observer sendctrl_0_observer = …; static const struct diag_observer sendctrl_1_observer = …; static ushort sdma_fetch_prio = …; module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO); MODULE_PARM_DESC(…) …; /* Besides logging QSFP events, we set appropriate TxDDS values */ static void init_txdds_table(struct qib_pportdata *ppd, int override); static void qsfp_7322_event(struct work_struct *work) { … } /* * There is little we can do but complain to the user if QSFP * initialization fails. */ static void qib_init_7322_qsfp(struct qib_pportdata *ppd) { … } /* * called at device initialization time, and also if the txselect * module parameter is changed. This is used for cables that don't * have valid QSFP EEPROMs (not present, or attenuation is zero). * We initialize to the default, then if there is a specific * unit,port match, we use that (and set it immediately, for the * current speed, if the link is at INIT or better). * String format is "default# unit#,port#=# ... u,p=#", separators must * be a SPACE character. A newline terminates. The u,p=# tuples may * optionally have "u,p=#,#", where the final # is the H1 value * The last specific match is used (actually, all are used, but last * one is the one that winds up set); if none at all, fall back on default. */ static void set_no_qsfp_atten(struct qib_devdata *dd, int change) { … } /* handle the txselect parameter changing */ static int setup_txselect(const char *str, const struct kernel_param *kp) { … } /* * Write the final few registers that depend on some of the * init setup. Done late in init, just before bringing up * the serdes. */ static int qib_late_7322_initreg(struct qib_devdata *dd) { … } /* per IB port errors. */ #define SENDCTRL_PIBP … #define RCVCTRL_PIBP … #define ERRS_PIBP … /* * Write the initialization per-port registers that need to be done at * driver load and after reset completes (i.e., that aren't done as part * of other init procedures called from qib_init.c). * Some of these should be redundant on reset, but play safe. */ static void write_7322_init_portregs(struct qib_pportdata *ppd) { … } /* * Write the initialization per-device registers that need to be done at * driver load and after reset completes (i.e., that aren't done as part * of other init procedures called from qib_init.c). Also write per-port * registers that are affected by overall device config, such as QP mapping * Some of these should be redundant on reset, but play safe. */ static void write_7322_initregs(struct qib_devdata *dd) { … } static int qib_init_7322_variables(struct qib_devdata *dd) { … } static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc, u32 *pbufnum) { … } static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv, u32 start) { … } /* * Must be called with sdma_lock held, or before init finished. */ static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt) { … } /* * sdma_lock should be acquired before calling this routine */ static void dump_sdma_7322_state(struct qib_pportdata *ppd) { … } static struct sdma_set_state_action sdma_7322_action_table[] = …; static void qib_7322_sdma_init_early(struct qib_pportdata *ppd) { … } static int init_sdma_7322_regs(struct qib_pportdata *ppd) { … } /* sdma_lock must be held */ static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd) { … } static int qib_sdma_7322_busy(struct qib_pportdata *ppd) { … } /* * Compute the amount of delay before sending the next packet if the * port's send rate differs from the static rate set for the QP. * The delay affects the next packet and the amount of the delay is * based on the length of the this packet. */ static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen, u8 srate, u8 vl) { … } /* * Enable the per-port VL15 send buffers for use. * They follow the rest of the buffers, without a config parameter. * This was in initregs, but that is done before the shadow * is set up, and this has to be done after the shadow is * set up. */ static void qib_7322_initvl15_bufs(struct qib_devdata *dd) { … } static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd) { … } #define QTXSLEEPS … static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start, u32 len, u32 which, struct qib_ctxtdata *rcd) { … } /* useful for trigger analyzers, etc. */ static void writescratch(struct qib_devdata *dd, u32 val) { … } /* Dummy for now, use chip regs soon */ static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum) { … } /** * qib_init_iba7322_funcs - set up the chip-specific function pointers * @pdev: the pci_dev for qlogic_ib device * @ent: pci_device_id struct for this dev * * Also allocates, inits, and returns the devdata struct for this * device instance * * This is global, and is called directly at init to set up the * chip-specific function pointers for later use. */ struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev, const struct pci_device_id *ent) { … } /* * Set the table entry at the specified index from the table specifed. * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR. * 'idx' below addresses the correct entry, while its 4 LSBs select the * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table. */ #define DDS_ENT_AMP_LSB … #define DDS_ENT_MAIN_LSB … #define DDS_ENT_POST_LSB … #define DDS_ENT_PRE_XTRA_LSB … #define DDS_ENT_PRE_LSB … /* * Set one entry in the TxDDS table for spec'd port * ridx picks one of the entries, while tp points * to the appropriate table entry. */ static void set_txdds(struct qib_pportdata *ppd, int ridx, const struct txdds_ent *tp) { … } static const struct vendor_txdds_ent vendor_txdds[] = …; static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = …; static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = …; static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = …; /* * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ. * These are mostly used for mez cards going through connectors * and backplane traces, but can be used to add other "unusual" * table values as well. */ static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = …; static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = …; static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = …; static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = …; static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds, unsigned atten) { … } /* * if override is set, the module parameter txselect has a value * for this specific port, so use it, rather than our normal mechanism. */ static void find_best_ent(struct qib_pportdata *ppd, const struct txdds_ent **sdr_dds, const struct txdds_ent **ddr_dds, const struct txdds_ent **qdr_dds, int override) { … } static void init_txdds_table(struct qib_pportdata *ppd, int override) { … } #define KR_AHB_ACC … #define KR_AHB_TRANS … #define AHB_TRANS_RDY … #define AHB_ADDR_LSB … #define AHB_DATA_LSB … #define AHB_WR … #define AHB_TRANS_TRIES … /* * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4, * 5=subsystem which is why most calls have "chan + chan >> 1" * for the channel argument. */ static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr, u32 data, u32 mask) { … } static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data, unsigned mask) { … } static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable) { … } static int serdes_7322_init(struct qib_pportdata *ppd) { … } static int serdes_7322_init_old(struct qib_pportdata *ppd) { … } static int serdes_7322_init_new(struct qib_pportdata *ppd) { … } /* start adjust QMH serdes parameters */ static void set_man_code(struct qib_pportdata *ppd, int chan, int code) { … } static void set_man_mode_h1(struct qib_pportdata *ppd, int chan, int enable, u32 tapenable) { … } /* Set clock to 1, 0, 1, 0 */ static void clock_man(struct qib_pportdata *ppd, int chan) { … } /* * write the current Tx serdes pre,post,main,amp settings into the serdes. * The caller must pass the settings appropriate for the current speed, * or not care if they are correct for the current speed. */ static void write_tx_serdes_param(struct qib_pportdata *ppd, struct txdds_ent *txdds) { … } /* * Set the parameters for mez cards on link bounce, so they are * always exactly what was requested. Similar logic to init_txdds * but does just the serdes. */ static void adj_tx_serdes(struct qib_pportdata *ppd) { … } /* set QDR forced value for H1, if needed */ static void force_h1(struct qib_pportdata *ppd) { … } #define SJA_EN … #define BISTEN_LSB … #define R_OPCODE_LSB … #define R_OP_NOP … #define R_OP_SHIFT … #define R_OP_UPDATE … #define R_TDI_LSB … #define R_TDO_LSB … #define R_RDY … static int qib_r_grab(struct qib_devdata *dd) { … } /* qib_r_wait_for_rdy() not only waits for the ready bit, it * returns the current state of R_TDO */ static int qib_r_wait_for_rdy(struct qib_devdata *dd) { … } static int qib_r_shift(struct qib_devdata *dd, int bisten, int len, u8 *inp, u8 *outp) { … } static int qib_r_update(struct qib_devdata *dd, int bisten) { … } #define BISTEN_PORT_SEL … #define LEN_PORT_SEL … #define BISTEN_AT … #define LEN_AT … #define BISTEN_ETM … #define LEN_ETM … #define BIT2BYTE(x) … /* these are common for all IB port use cases. */ static u8 reset_at[BIT2BYTE(LEN_AT)] = …; static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = …; static u8 at[BIT2BYTE(LEN_AT)] = …; /* used for IB1 or IB2, only one in use */ static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = …; /* used when both IB1 and IB2 are in use */ static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = …; /* used when only IB1 is in use */ static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = …; /* used when only IB2 is in use */ static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = …; /* used when both IB1 and IB2 are in use */ static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = …; /* * Do setup to properly handle IB link recovery; if port is zero, we * are initializing to cover both ports; otherwise we are initializing * to cover a single port card, or the port has reached INIT and we may * need to switch coverage types. */ static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both) { … } static void check_7322_rxe_status(struct qib_pportdata *ppd) { … }
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