linux/drivers/infiniband/hw/irdma/i40iw_hw.h

/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2015 - 2021 Intel Corporation */
#ifndef I40IW_HW_H
#define I40IW_HW_H
#define I40E_VFPE_CQPTAIL1
#define I40E_VFPE_CQPDB1
#define I40E_VFPE_CCQPSTATUS1
#define I40E_VFPE_CCQPHIGH1
#define I40E_VFPE_CCQPLOW1
#define I40E_VFPE_CQARM1
#define I40E_VFPE_CQACK1
#define I40E_VFPE_AEQALLOC1
#define I40E_VFPE_CQPERRCODES1
#define I40E_VFPE_WQEALLOC1
#define I40E_VFINT_DYN_CTLN(_INTVF)

#define I40E_PFPE_CQPTAIL

#define I40E_PFPE_CQPDB
#define I40E_PFPE_CCQPSTATUS
#define I40E_PFPE_CCQPHIGH
#define I40E_PFPE_CCQPLOW
#define I40E_PFPE_CQARM
#define I40E_PFPE_CQACK
#define I40E_PFPE_AEQALLOC
#define I40E_PFPE_CQPERRCODES
#define I40E_PFPE_WQEALLOC
#define I40E_GLPCI_LBARCTRL
#define I40E_GLPE_CPUSTATUS0
#define I40E_GLPE_CPUSTATUS1
#define I40E_GLPE_CPUSTATUS2
#define I40E_GLPE_CRITERR
#define I40E_PFHMC_PDINV
#define I40E_GLHMC_VFPDINV(_i)
#define I40E_PFINT_DYN_CTLN(_INTPF)
#define I40E_PFINT_AEQCTL

#define I40E_GLPES_PFIP4RXDISCARD(_i)
#define I40E_GLPES_PFIP4RXTRUNC(_i)
#define I40E_GLPES_PFIP4TXNOROUTE(_i)
#define I40E_GLPES_PFIP6RXDISCARD(_i)
#define I40E_GLPES_PFIP6RXTRUNC(_i)

#define I40E_GLPES_PFRDMAVBNDLO(_i)
#define I40E_GLPES_PFIP4TXMCOCTSLO(_i)
#define I40E_GLPES_PFIP6RXMCOCTSLO(_i)
#define I40E_GLPES_PFIP6TXMCOCTSLO(_i)
#define I40E_GLPES_PFUDPRXPKTSLO(_i)
#define I40E_GLPES_PFUDPTXPKTSLO(_i)

#define I40E_GLPES_PFIP6TXNOROUTE(_i)
#define I40E_GLPES_PFTCPRTXSEG(_i)
#define I40E_GLPES_PFTCPRXOPTERR(_i)
#define I40E_GLPES_PFTCPRXPROTOERR(_i)
#define I40E_GLPES_PFRXVLANERR(_i)
#define I40E_GLPES_PFIP4RXOCTSLO(_i)
#define I40E_GLPES_PFIP4RXPKTSLO(_i)
#define I40E_GLPES_PFIP4RXFRAGSLO(_i)
#define I40E_GLPES_PFIP4RXMCPKTSLO(_i)
#define I40E_GLPES_PFIP4TXOCTSLO(_i)
#define I40E_GLPES_PFIP4TXPKTSLO(_i)
#define I40E_GLPES_PFIP4TXFRAGSLO(_i)
#define I40E_GLPES_PFIP4TXMCPKTSLO(_i)
#define I40E_GLPES_PFIP6RXOCTSLO(_i)
#define I40E_GLPES_PFIP6RXPKTSLO(_i)
#define I40E_GLPES_PFIP6RXFRAGSLO(_i)
#define I40E_GLPES_PFIP6TXOCTSLO(_i)
#define I40E_GLPES_PFIP6TXPKTSLO(_i)
#define I40E_GLPES_PFIP6TXFRAGSLO(_i)
#define I40E_GLPES_PFIP6TXMCPKTSLO(_i)
#define I40E_GLPES_PFTCPTXSEGLO(_i)
#define I40E_GLPES_PFRDMARXRDSLO(_i)
#define I40E_GLPES_PFRDMARXSNDSLO(_i)
#define I40E_GLPES_PFRDMARXWRSLO(_i)
#define I40E_GLPES_PFRDMATXRDSLO(_i)
#define I40E_GLPES_PFRDMATXSNDSLO(_i)
#define I40E_GLPES_PFRDMATXWRSLO(_i)
#define I40E_GLPES_PFIP4RXMCOCTSLO(_i)
#define I40E_GLPES_PFIP6RXMCPKTSLO(_i)
#define I40E_GLPES_PFTCPRXSEGSLO(_i)
#define I40E_GLPES_PFRDMAVINVLO(_i)

#define I40IW_DB_ADDR_OFFSET

#define I40IW_VF_DB_ADDR_OFFSET

#define I40E_PFINT_LNKLSTN(_INTPF)
#define I40E_PFINT_LNKLSTN_MAX_INDEX
#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX
#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE

#define I40E_PFINT_CEQCTL(_INTPF)
#define I40E_PFINT_CEQCTL_MAX_INDEX

/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
#define I40E_PFINT_CEQCTL_MSIX_INDX_S
#define I40E_PFINT_CEQCTL_MSIX_INDX
#define I40E_PFINT_CEQCTL_ITR_INDX_S
#define I40E_PFINT_CEQCTL_ITR_INDX
#define I40E_PFINT_CEQCTL_MSIX0_INDX_S
#define I40E_PFINT_CEQCTL_MSIX0_INDX
#define I40E_PFINT_CEQCTL_NEXTQ_INDX_S
#define I40E_PFINT_CEQCTL_NEXTQ_INDX
#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_S
#define I40E_PFINT_CEQCTL_NEXTQ_TYPE
#define I40E_PFINT_CEQCTL_CAUSE_ENA_S
#define I40E_PFINT_CEQCTL_CAUSE_ENA
#define I40E_PFINT_CEQCTL_INTEVENT_S
#define I40E_PFINT_CEQCTL_INTEVENT
#define I40E_CQPSQ_STAG_PDID_S
#define I40E_CQPSQ_STAG_PDID
#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_S
#define I40E_PFPE_CCQPSTATUS_CCQP_DONE
#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_S
#define I40E_PFPE_CCQPSTATUS_CCQP_ERR
#define I40E_PFINT_DYN_CTLN_ITR_INDX_S
#define I40E_PFINT_DYN_CTLN_ITR_INDX
#define I40E_PFINT_DYN_CTLN_INTENA_S
#define I40E_PFINT_DYN_CTLN_INTENA
#define I40E_CQPSQ_CQ_CEQID_S
#define I40E_CQPSQ_CQ_CEQID
#define I40E_CQPSQ_CQ_CQID_S
#define I40E_CQPSQ_CQ_CQID
#define I40E_COMMIT_FPM_CQCNT_S
#define I40E_COMMIT_FPM_CQCNT

#define I40E_VSIQF_CTL(_VSI)

enum i40iw_device_caps_const {};

#define I40IW_QP_WQE_MIN_SIZE
#define I40IW_QP_WQE_MAX_SIZE
#define I40IW_MAX_RQ_WQE_SHIFT
#define I40IW_MAX_QUANTA_PER_WR

#define I40IW_QP_SW_MAX_SQ_QUANTA
#define I40IW_QP_SW_MAX_RQ_QUANTA
#define I40IW_QP_SW_MAX_WQ_QUANTA
#define I40IW_MAX_QP_WRS
#define I40IW_FIRST_VF_FPM_ID
#define QUEUE_TYPE_CEQ
#define NULL_QUEUE_INDEX

void i40iw_init_hw(struct irdma_sc_dev *dev);
#endif /* I40IW_HW_H */