linux/drivers/infiniband/hw/irdma/icrdma_hw.h

/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
/* Copyright (c) 2017 - 2021 Intel Corporation */
#ifndef ICRDMA_HW_H
#define ICRDMA_HW_H

#include "irdma.h"

#define VFPE_CQPTAIL1 …
#define VFPE_CQPDB1 …
#define VFPE_CCQPSTATUS1 …
#define VFPE_CCQPHIGH1 …
#define VFPE_CCQPLOW1 …
#define VFPE_CQARM1 …
#define VFPE_CQARM1 …
#define VFPE_CQACK1 …
#define VFPE_AEQALLOC1 …
#define VFPE_CQPERRCODES1 …
#define VFPE_WQEALLOC1 …
#define VFINT_DYN_CTLN(_i) …

#define PFPE_CQPTAIL …
#define PFPE_CQPDB …
#define PFPE_CCQPSTATUS …
#define PFPE_CCQPHIGH …
#define PFPE_CCQPLOW …
#define PFPE_CQARM …
#define PFPE_CQACK …
#define PFPE_AEQALLOC …
#define GLINT_DYN_CTL(_INT) …
#define GLPCI_LBARCTRL …
#define GLPE_CPUSTATUS0 …
#define GLPE_CPUSTATUS1 …
#define GLPE_CPUSTATUS2 …
#define PFINT_AEQCTL …
#define PFPE_CQPERRCODES …
#define PFPE_WQEALLOC …
#define GLINT_CEQCTL(_INT) …
#define VSIQF_PE_CTL1(_VSI) …
#define PFHMC_PDINV …
#define GLHMC_VFPDINV(_i) …
#define GLPE_CRITERR …
#define GLINT_RATE(_INT) …

#define ICRDMA_DB_ADDR_OFFSET …

#define ICRDMA_VF_DB_ADDR_OFFSET …

/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */
#define ICRDMA_CCQPSTATUS_CCQP_DONE_S …
#define ICRDMA_CCQPSTATUS_CCQP_DONE …
#define ICRDMA_CCQPSTATUS_CCQP_ERR_S …
#define ICRDMA_CCQPSTATUS_CCQP_ERR …
#define ICRDMA_CQPSQ_STAG_PDID_S …
#define ICRDMA_CQPSQ_STAG_PDID …
#define ICRDMA_CQPSQ_CQ_CEQID_S …
#define ICRDMA_CQPSQ_CQ_CEQID …
#define ICRDMA_CQPSQ_CQ_CQID_S …
#define ICRDMA_CQPSQ_CQ_CQID …
#define ICRDMA_COMMIT_FPM_CQCNT_S …
#define ICRDMA_COMMIT_FPM_CQCNT …

enum icrdma_device_caps_const { … };

void icrdma_init_hw(struct irdma_sc_dev *dev);
#endif /* ICRDMA_HW_H*/