/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* * Copyright(c) 2015 - 2020 Intel Corporation. */ #ifndef _CHIP_H #define _CHIP_H /* * This file contains all of the defines that is specific to the HFI chip */ /* sizes */ #define BITS_PER_REGISTER … #define NUM_INTERRUPT_SOURCES … #define RXE_NUM_CONTEXTS … #define RXE_PER_CONTEXT_SIZE … #define RXE_NUM_TID_FLOWS … #define RXE_NUM_DATA_VL … #define TXE_NUM_CONTEXTS … #define TXE_NUM_SDMA_ENGINES … #define NUM_CONTEXTS_PER_SET … #define VL_ARB_HIGH_PRIO_TABLE_SIZE … #define VL_ARB_LOW_PRIO_TABLE_SIZE … #define VL_ARB_TABLE_SIZE … #define TXE_NUM_32_BIT_COUNTER … #define TXE_NUM_64_BIT_COUNTER … #define TXE_NUM_DATA_VL … #define TXE_PIO_SIZE … #define PIO_BLOCK_SIZE … #define SDMA_BLOCK_SIZE … #define RCV_BUF_BLOCK_SIZE … #define PIO_CMASK … #define MAX_EAGER_ENTRIES … #define MAX_TID_PAIR_ENTRIES … /* * Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed * at 64 bytes for all generation one devices */ #define CM_VAU … /* HFI link credit count, AKA receive buffer depth (RBUF_DEPTH) */ #define CM_GLOBAL_CREDITS … /* Number of PKey entries in the HW */ #define MAX_PKEY_VALUES … #include "chip_registers.h" #define RXE_PER_CONTEXT_USER … #define TXE_PIO_SEND … /* PBC flags */ #define PBC_INTR … #define PBC_DC_INFO_SHIFT … #define PBC_DC_INFO … #define PBC_TEST_EBP … #define PBC_PACKET_BYPASS … #define PBC_CREDIT_RETURN … #define PBC_INSERT_BYPASS_ICRC … #define PBC_TEST_BAD_ICRC … #define PBC_FECN … /* PbcInsertHcrc field settings */ #define PBC_IHCRC_LKDETH … #define PBC_IHCRC_GKDETH … #define PBC_IHCRC_NONE … /* PBC fields */ #define PBC_STATIC_RATE_CONTROL_COUNT_SHIFT … #define PBC_STATIC_RATE_CONTROL_COUNT_MASK … #define PBC_STATIC_RATE_CONTROL_COUNT_SMASK … #define PBC_INSERT_HCRC_SHIFT … #define PBC_INSERT_HCRC_MASK … #define PBC_INSERT_HCRC_SMASK … #define PBC_VL_SHIFT … #define PBC_VL_MASK … #define PBC_VL_SMASK … #define PBC_LENGTH_DWS_SHIFT … #define PBC_LENGTH_DWS_MASK … #define PBC_LENGTH_DWS_SMASK … /* Credit Return Fields */ #define CR_COUNTER_SHIFT … #define CR_COUNTER_MASK … #define CR_COUNTER_SMASK … #define CR_STATUS_SHIFT … #define CR_STATUS_MASK … #define CR_STATUS_SMASK … #define CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT … #define CR_CREDIT_RETURN_DUE_TO_PBC_MASK … #define CR_CREDIT_RETURN_DUE_TO_PBC_SMASK … #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT … #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK … #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK … #define CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT … #define CR_CREDIT_RETURN_DUE_TO_ERR_MASK … #define CR_CREDIT_RETURN_DUE_TO_ERR_SMASK … #define CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT … #define CR_CREDIT_RETURN_DUE_TO_FORCE_MASK … #define CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK … /* Specific IRQ sources */ #define CCE_ERR_INT … #define RXE_ERR_INT … #define MISC_ERR_INT … #define PIO_ERR_INT … #define SDMA_ERR_INT … #define EGRESS_ERR_INT … #define TXE_ERR_INT … #define PBC_INT … #define GPIO_ASSERT_INT … #define QSFP1_INT … #define QSFP2_INT … #define TCRIT_INT … /* interrupt source ranges */ #define IS_FIRST_SOURCE … #define IS_GENERAL_ERR_START … #define IS_SDMAENG_ERR_START … #define IS_SENDCTXT_ERR_START … #define IS_SDMA_START … #define IS_SDMA_PROGRESS_START … #define IS_SDMA_IDLE_START … #define IS_VARIOUS_START … #define IS_DC_START … #define IS_RCVAVAIL_START … #define IS_RCVURGENT_START … #define IS_SENDCREDIT_START … #define IS_RESERVED_START … #define IS_LAST_SOURCE … /* derived interrupt source values */ #define IS_GENERAL_ERR_END … #define IS_SDMAENG_ERR_END … #define IS_SENDCTXT_ERR_END … #define IS_SDMA_END … #define IS_SDMA_PROGRESS_END … #define IS_SDMA_IDLE_END … #define IS_VARIOUS_END … #define IS_DC_END … #define IS_RCVAVAIL_END … #define IS_RCVURGENT_END … #define IS_SENDCREDIT_END … #define IS_RESERVED_END … /* DCC_CFG_PORT_CONFIG logical link states */ #define LSTATE_DOWN … #define LSTATE_INIT … #define LSTATE_ARMED … #define LSTATE_ACTIVE … /* DCC_CFG_RESET reset states */ #define LCB_RX_FPE_TX_FPE_INTO_RESET … /* 0x17 */ #define LCB_RX_FPE_TX_FPE_OUT_OF_RESET … /* DC8051_STS_CUR_STATE port values (physical link states) */ #define PLS_DISABLED … #define PLS_OFFLINE … #define PLS_OFFLINE_QUIET … #define PLS_OFFLINE_PLANNED_DOWN_INFORM … #define PLS_OFFLINE_READY_TO_QUIET_LT … #define PLS_OFFLINE_REPORT_FAILURE … #define PLS_OFFLINE_READY_TO_QUIET_BCC … #define PLS_OFFLINE_QUIET_DURATION … #define PLS_POLLING … #define PLS_POLLING_QUIET … #define PLS_POLLING_ACTIVE … #define PLS_CONFIGPHY … #define PLS_CONFIGPHY_DEBOUCE … #define PLS_CONFIGPHY_ESTCOMM … #define PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT … #define PLS_CONFIGPHY_ESTCOMM_LOCAL_COMPLETE … #define PLS_CONFIGPHY_OPTEQ … #define PLS_CONFIGPHY_OPTEQ_OPTIMIZING … #define PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE … #define PLS_CONFIGPHY_VERIFYCAP … #define PLS_CONFIGPHY_VERIFYCAP_EXCHANGE … #define PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE … #define PLS_CONFIGLT … #define PLS_CONFIGLT_CONFIGURE … #define PLS_CONFIGLT_LINK_TRANSFER_ACTIVE … #define PLS_LINKUP … #define PLS_PHYTEST … #define PLS_INTERNAL_SERDES_LOOPBACK … #define PLS_QUICK_LINKUP … /* DC_DC8051_CFG_HOST_CMD_0.REQ_TYPE - 8051 host commands */ #define HCMD_LOAD_CONFIG_DATA … #define HCMD_READ_CONFIG_DATA … #define HCMD_CHANGE_PHY_STATE … #define HCMD_SEND_LCB_IDLE_MSG … #define HCMD_MISC … #define HCMD_READ_LCB_IDLE_MSG … #define HCMD_READ_LCB_CSR … #define HCMD_WRITE_LCB_CSR … #define HCMD_INTERFACE_TEST … /* DC_DC8051_CFG_HOST_CMD_1.RETURN_CODE - 8051 host command return */ #define HCMD_SUCCESS … /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR - error flags */ #define SPICO_ROM_FAILED … #define UNKNOWN_FRAME … #define TARGET_BER_NOT_MET … #define FAILED_SERDES_INTERNAL_LOOPBACK … #define FAILED_SERDES_INIT … #define FAILED_LNI_POLLING … #define FAILED_LNI_DEBOUNCE … #define FAILED_LNI_ESTBCOMM … #define FAILED_LNI_OPTEQ … #define FAILED_LNI_VERIFY_CAP1 … #define FAILED_LNI_VERIFY_CAP2 … #define FAILED_LNI_CONFIGLT … #define HOST_HANDSHAKE_TIMEOUT … #define EXTERNAL_DEVICE_REQ_TIMEOUT … #define FAILED_LNI … /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG - host message flags */ #define HOST_REQ_DONE … #define BC_PWR_MGM_MSG … #define BC_SMA_MSG … #define BC_BCC_UNKNOWN_MSG … #define BC_IDLE_UNKNOWN_MSG … #define EXT_DEVICE_CFG_REQ … #define VERIFY_CAP_FRAME … #define LINKUP_ACHIEVED … #define LINK_GOING_DOWN … #define LINK_WIDTH_DOWNGRADED … /* DC_DC8051_CFG_EXT_DEV_1.REQ_TYPE - 8051 host requests */ #define HREQ_LOAD_CONFIG … #define HREQ_SAVE_CONFIG … #define HREQ_READ_CONFIG … #define HREQ_SET_TX_EQ_ABS … #define HREQ_SET_TX_EQ_REL … #define HREQ_ENABLE … #define HREQ_LCB_RESET … #define HREQ_CONFIG_DONE … #define HREQ_INTERFACE_TEST … /* DC_DC8051_CFG_EXT_DEV_0.RETURN_CODE - 8051 host request return codes */ #define HREQ_INVALID … #define HREQ_SUCCESS … #define HREQ_NOT_SUPPORTED … #define HREQ_FEATURE_NOT_SUPPORTED … #define HREQ_REQUEST_REJECTED … #define HREQ_EXECUTION_ONGOING … /* MISC host command functions */ #define HCMD_MISC_REQUEST_LCB_ACCESS … #define HCMD_MISC_GRANT_LCB_ACCESS … /* idle flit message types */ #define IDLE_PHYSICAL_LINK_MGMT … #define IDLE_CRU … #define IDLE_SMA … #define IDLE_POWER_MGMT … /* idle flit message send fields (both send and read) */ #define IDLE_PAYLOAD_MASK … #define IDLE_PAYLOAD_SHIFT … #define IDLE_MSG_TYPE_MASK … #define IDLE_MSG_TYPE_SHIFT … /* idle flit message read fields */ #define READ_IDLE_MSG_TYPE_MASK … #define READ_IDLE_MSG_TYPE_SHIFT … /* SMA idle flit payload commands */ #define SMA_IDLE_ARM … #define SMA_IDLE_ACTIVE … /* DC_DC8051_CFG_MODE.GENERAL bits */ #define DISABLE_SELF_GUID_CHECK … /* Bad L2 frame error code */ #define BAD_L2_ERR … /* * Eager buffer minimum and maximum sizes supported by the hardware. * All power-of-two sizes in between are supported as well. * MAX_EAGER_BUFFER_TOTAL is the maximum size of memory * allocatable for Eager buffer to a single context. All others * are limits for the RcvArray entries. */ #define MIN_EAGER_BUFFER … #define MAX_EAGER_BUFFER … #define MAX_EAGER_BUFFER_TOTAL … #define MAX_EXPECTED_BUFFER … #define HFI1_MIN_HDRQ_EGRBUF_CNT … #define HFI1_MAX_HDRQ_EGRBUF_CNT … /* * Receive expected base and count and eager base and count increment - * the CSR fields hold multiples of this value. */ #define RCV_SHIFT … #define RCV_INCREMENT … /* * Receive header queue entry increment - the CSR holds multiples of * this value. */ #define HDRQ_SIZE_SHIFT … #define HDRQ_INCREMENT … /* * Freeze handling flags */ #define FREEZE_ABORT … #define FREEZE_SELF … #define FREEZE_LINK_DOWN … /* * Chip implementation codes. */ #define ICODE_RTL_SILICON … #define ICODE_RTL_VCS_SIMULATION … #define ICODE_FPGA_EMULATION … #define ICODE_FUNCTIONAL_SIMULATOR … /* * 8051 data memory size. */ #define DC8051_DATA_MEM_SIZE … /* * 8051 firmware registers */ #define NUM_GENERAL_FIELDS … #define NUM_LANE_FIELDS … /* 8051 general register Field IDs */ #define LINK_OPTIMIZATION_SETTINGS … #define LINK_TUNING_PARAMETERS … #define DC_HOST_COMM_SETTINGS … #define TX_SETTINGS … #define VERIFY_CAP_LOCAL_PHY … #define VERIFY_CAP_LOCAL_FABRIC … #define VERIFY_CAP_LOCAL_LINK_MODE … #define LOCAL_DEVICE_ID … #define RESERVED_REGISTERS … #define LOCAL_LNI_INFO … #define REMOTE_LNI_INFO … #define MISC_STATUS … #define VERIFY_CAP_REMOTE_PHY … #define VERIFY_CAP_REMOTE_FABRIC … #define VERIFY_CAP_REMOTE_LINK_WIDTH … #define LAST_LOCAL_STATE_COMPLETE … #define LAST_REMOTE_STATE_COMPLETE … #define LINK_QUALITY_INFO … #define REMOTE_DEVICE_ID … #define LINK_DOWN_REASON … #define VERSION_PATCH … /* 8051 lane specific register field IDs */ #define TX_EQ_SETTINGS … #define CHANNEL_LOSS_SETTINGS … /* Lane ID for general configuration registers */ #define GENERAL_CONFIG … /* LINK_TUNING_PARAMETERS fields */ #define TUNING_METHOD_SHIFT … /* LINK_OPTIMIZATION_SETTINGS fields */ #define ENABLE_EXT_DEV_CONFIG_SHIFT … /* LOAD_DATA 8051 command shifts and fields */ #define LOAD_DATA_FIELD_ID_SHIFT … #define LOAD_DATA_FIELD_ID_MASK … #define LOAD_DATA_LANE_ID_SHIFT … #define LOAD_DATA_LANE_ID_MASK … #define LOAD_DATA_DATA_SHIFT … #define LOAD_DATA_DATA_MASK … /* READ_DATA 8051 command shifts and fields */ #define READ_DATA_FIELD_ID_SHIFT … #define READ_DATA_FIELD_ID_MASK … #define READ_DATA_LANE_ID_SHIFT … #define READ_DATA_LANE_ID_MASK … #define READ_DATA_DATA_SHIFT … #define READ_DATA_DATA_MASK … /* TX settings fields */ #define ENABLE_LANE_TX_SHIFT … #define ENABLE_LANE_TX_MASK … #define TX_POLARITY_INVERSION_SHIFT … #define TX_POLARITY_INVERSION_MASK … #define RX_POLARITY_INVERSION_SHIFT … #define RX_POLARITY_INVERSION_MASK … #define MAX_RATE_SHIFT … #define MAX_RATE_MASK … /* verify capability PHY fields */ #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT … #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK … #define POWER_MANAGEMENT_SHIFT … #define POWER_MANAGEMENT_MASK … /* 8051 lane register Field IDs */ #define SPICO_FW_VERSION … /* SPICO firmware version fields */ #define SPICO_ROM_VERSION_SHIFT … #define SPICO_ROM_VERSION_MASK … #define SPICO_ROM_PROD_ID_SHIFT … #define SPICO_ROM_PROD_ID_MASK … /* verify capability fabric fields */ #define VAU_SHIFT … #define VAU_MASK … #define Z_SHIFT … #define Z_MASK … #define VCU_SHIFT … #define VCU_MASK … #define VL15BUF_SHIFT … #define VL15BUF_MASK … #define CRC_SIZES_SHIFT … #define CRC_SIZES_MASK … /* verify capability local link width fields */ #define LINK_WIDTH_SHIFT … #define LINK_WIDTH_MASK … #define LOCAL_FLAG_BITS_SHIFT … #define LOCAL_FLAG_BITS_MASK … #define MISC_CONFIG_BITS_SHIFT … #define MISC_CONFIG_BITS_MASK … /* verify capability remote link width fields */ #define REMOTE_TX_RATE_SHIFT … #define REMOTE_TX_RATE_MASK … /* LOCAL_DEVICE_ID fields */ #define LOCAL_DEVICE_REV_SHIFT … #define LOCAL_DEVICE_REV_MASK … #define LOCAL_DEVICE_ID_SHIFT … #define LOCAL_DEVICE_ID_MASK … /* REMOTE_DEVICE_ID fields */ #define REMOTE_DEVICE_REV_SHIFT … #define REMOTE_DEVICE_REV_MASK … #define REMOTE_DEVICE_ID_SHIFT … #define REMOTE_DEVICE_ID_MASK … /* local LNI link width fields */ #define ENABLE_LANE_RX_SHIFT … #define ENABLE_LANE_RX_MASK … /* mask, shift for reading 'mgmt_enabled' value from REMOTE_LNI_INFO field */ #define MGMT_ALLOWED_SHIFT … #define MGMT_ALLOWED_MASK … /* mask, shift for 'link_quality' within LINK_QUALITY_INFO field */ #define LINK_QUALITY_SHIFT … #define LINK_QUALITY_MASK … /* * mask, shift for reading 'planned_down_remote_reason_code' * from LINK_QUALITY_INFO field */ #define DOWN_REMOTE_REASON_SHIFT … #define DOWN_REMOTE_REASON_MASK … #define HOST_INTERFACE_VERSION … #define HOST_INTERFACE_VERSION_SHIFT … #define HOST_INTERFACE_VERSION_MASK … /* verify capability PHY power management bits */ #define PWRM_BER_CONTROL … #define PWRM_BANDWIDTH_CONTROL … /* 8051 link down reasons */ #define LDR_LINK_TRANSFER_ACTIVE_LOW … #define LDR_RECEIVED_LINKDOWN_IDLE_MSG … #define LDR_RECEIVED_HOST_OFFLINE_REQ … /* verify capability fabric CRC size bits */ enum { … }; #define SUPPORTED_CRCS … /* misc status version fields */ #define STS_FM_VERSION_MINOR_SHIFT … #define STS_FM_VERSION_MINOR_MASK … #define STS_FM_VERSION_MAJOR_SHIFT … #define STS_FM_VERSION_MAJOR_MASK … #define STS_FM_VERSION_PATCH_SHIFT … #define STS_FM_VERSION_PATCH_MASK … /* LCB_CFG_CRC_MODE TX_VAL and RX_VAL CRC mode values */ #define LCB_CRC_16B … #define LCB_CRC_14B … #define LCB_CRC_48B … #define LCB_CRC_12B_16B_PER_LANE … /* * the following enum is (almost) a copy/paste of the definition * in the OPA spec, section 20.2.2.6.8 (PortInfo) */ enum { … }; /* timeouts */ #define LINK_RESTART_DELAY … #define TIMEOUT_8051_START … #define DC8051_COMMAND_TIMEOUT … #define FREEZE_STATUS_TIMEOUT … #define VL_STATUS_CLEAR_TIMEOUT … #define CCE_STATUS_TIMEOUT … /* cclock tick time, in picoseconds per tick: 1/speed * 10^12 */ #define ASIC_CCLOCK_PS … #define FPGA_CCLOCK_PS … /* * Mask of enabled MISC errors. Do not enable the two RSA engine errors - * see firmware.c:run_rsa() for details. */ #define DRIVER_MISC_MASK … /* valid values for the loopback module parameter */ #define LOOPBACK_NONE … #define LOOPBACK_SERDES … #define LOOPBACK_LCB … #define LOOPBACK_CABLE … /* set up bits in MISC_CONFIG_BITS */ #define LOOPBACK_SERDES_CONFIG_BIT_MASK_SHIFT … #define EXT_CFG_LCB_RESET_SUPPORTED_SHIFT … /* read and write hardware registers */ u64 read_csr(const struct hfi1_devdata *dd, u32 offset); void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value); /* * The *_kctxt_* flavor of the CSR read/write functions are for * per-context or per-SDMA CSRs that are not mappable to user-space. * Their spacing is not a PAGE_SIZE multiple. */ static inline u64 read_kctxt_csr(const struct hfi1_devdata *dd, int ctxt, u32 offset0) { … } static inline void write_kctxt_csr(struct hfi1_devdata *dd, int ctxt, u32 offset0, u64 value) { … } int read_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 *data); int write_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 data); void __iomem *get_csr_addr( const struct hfi1_devdata *dd, u32 offset); static inline void __iomem *get_kctxt_csr_addr( const struct hfi1_devdata *dd, int ctxt, u32 offset0) { … } /* * The *_uctxt_* flavor of the CSR read/write functions are for * per-context CSRs that are mappable to user space. All these CSRs * are spaced by a PAGE_SIZE multiple in order to be mappable to * different processes without exposing other contexts' CSRs */ static inline u64 read_uctxt_csr(const struct hfi1_devdata *dd, int ctxt, u32 offset0) { … } static inline void write_uctxt_csr(struct hfi1_devdata *dd, int ctxt, u32 offset0, u64 value) { … } static inline u32 chip_rcv_contexts(struct hfi1_devdata *dd) { … } static inline u32 chip_send_contexts(struct hfi1_devdata *dd) { … } static inline u32 chip_sdma_engines(struct hfi1_devdata *dd) { … } static inline u32 chip_pio_mem_size(struct hfi1_devdata *dd) { … } static inline u32 chip_sdma_mem_size(struct hfi1_devdata *dd) { … } static inline u32 chip_rcv_array_count(struct hfi1_devdata *dd) { … } u8 encode_rcv_header_entry_size(u8 size); int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt); void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt); u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl, u32 dw_len); /* firmware.c */ #define SBUS_MASTER_BROADCAST … #define NUM_PCIE_SERDES … extern const u8 pcie_serdes_broadcast[]; extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES]; /* SBus commands */ #define RESET_SBUS_RECEIVER … #define WRITE_SBUS_RECEIVER … #define READ_SBUS_RECEIVER … void sbus_request(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr, u8 command, u32 data_in); int sbus_request_slow(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr, u8 command, u32 data_in); void set_sbus_fast_mode(struct hfi1_devdata *dd); void clear_sbus_fast_mode(struct hfi1_devdata *dd); int hfi1_firmware_init(struct hfi1_devdata *dd); int load_pcie_firmware(struct hfi1_devdata *dd); int load_firmware(struct hfi1_devdata *dd); void dispose_firmware(void); int acquire_hw_mutex(struct hfi1_devdata *dd); void release_hw_mutex(struct hfi1_devdata *dd); /* * Bitmask of dynamic access for ASIC block chip resources. Each HFI has its * own range of bits for the resource so it can clear its own bits on * starting and exiting. If either HFI has the resource bit set, the * resource is in use. The separate bit ranges are: * HFI0 bits 7:0 * HFI1 bits 15:8 */ #define CR_SBUS … #define CR_EPROM … #define CR_I2C1 … #define CR_I2C2 … #define CR_DYN_SHIFT … #define CR_DYN_MASK … /* * Bitmask of static ASIC states these are outside of the dynamic ASIC * block chip resources above. These are to be set once and never cleared. * Must be holding the SBus dynamic flag when setting. */ #define CR_THERM_INIT … int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait); void release_chip_resource(struct hfi1_devdata *dd, u32 resource); bool check_chip_resource(struct hfi1_devdata *dd, u32 resource, const char *func); void init_chip_resources(struct hfi1_devdata *dd); void finish_chip_resources(struct hfi1_devdata *dd); /* ms wait time for access to an SBus resoure */ #define SBUS_TIMEOUT … /* ms wait time for a qsfp (i2c) chain to become available */ #define QSFP_WAIT … void fabric_serdes_reset(struct hfi1_devdata *dd); int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result); /* chip.c */ void read_misc_status(struct hfi1_devdata *dd, u8 *ver_major, u8 *ver_minor, u8 *ver_patch); int write_host_interface_version(struct hfi1_devdata *dd, u8 version); void read_guid(struct hfi1_devdata *dd); int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout); void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason, u8 neigh_reason, u8 rem_reason); int set_link_state(struct hfi1_pportdata *, u32 state); int port_ltp_to_cap(int port_ltp); void handle_verify_cap(struct work_struct *work); void handle_freeze(struct work_struct *work); void handle_link_up(struct work_struct *work); void handle_link_down(struct work_struct *work); void handle_link_downgrade(struct work_struct *work); void handle_link_bounce(struct work_struct *work); void handle_start_link(struct work_struct *work); void handle_sma_message(struct work_struct *work); int reset_qsfp(struct hfi1_pportdata *ppd); void qsfp_event(struct work_struct *work); void start_freeze_handling(struct hfi1_pportdata *ppd, int flags); int send_idle_sma(struct hfi1_devdata *dd, u64 message); int load_8051_config(struct hfi1_devdata *, u8, u8, u32); int read_8051_config(struct hfi1_devdata *, u8, u8, u32 *); int start_link(struct hfi1_pportdata *ppd); int bringup_serdes(struct hfi1_pportdata *ppd); void set_intr_state(struct hfi1_devdata *dd, u32 enable); bool apply_link_downgrade_policy(struct hfi1_pportdata *ppd, bool refresh_widths); void update_usrhead(struct hfi1_ctxtdata *rcd, u32 hd, u32 updegr, u32 egrhd, u32 intr_adjust, u32 npkts); int stop_drain_data_vls(struct hfi1_devdata *dd); int open_fill_data_vls(struct hfi1_devdata *dd); u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns); u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclock); void get_linkup_link_widths(struct hfi1_pportdata *ppd); void read_ltp_rtt(struct hfi1_devdata *dd); void clear_linkup_counters(struct hfi1_devdata *dd); u32 hdrqempty(struct hfi1_ctxtdata *rcd); int is_ax(struct hfi1_devdata *dd); int is_bx(struct hfi1_devdata *dd); bool is_urg_masked(struct hfi1_ctxtdata *rcd); u32 read_physical_state(struct hfi1_devdata *dd); u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate); const char *opa_lstate_name(u32 lstate); const char *opa_pstate_name(u32 pstate); u32 driver_pstate(struct hfi1_pportdata *ppd); u32 driver_lstate(struct hfi1_pportdata *ppd); int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok); int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok); #define LCB_START … #define LCB_END … extern uint num_vls; extern uint disable_integrity; u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl); u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data); u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl); u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data); u32 read_logical_state(struct hfi1_devdata *dd); void force_recv_intr(struct hfi1_ctxtdata *rcd); /* Per VL indexes */ enum { … }; static inline int vl_from_idx(int idx) { … } static inline int idx_from_vl(int vl) { … } /* Per device counter indexes */ enum { … }; /* Per port counter indexes */ enum { … }; u64 get_all_cpu_total(u64 __percpu *cntr); void hfi1_start_cleanup(struct hfi1_devdata *dd); void hfi1_clear_tids(struct hfi1_ctxtdata *rcd); void hfi1_init_ctxt(struct send_context *sc); void hfi1_put_tid(struct hfi1_devdata *dd, u32 index, u32 type, unsigned long pa, u16 order); void hfi1_quiet_serdes(struct hfi1_pportdata *ppd); void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, struct hfi1_ctxtdata *rcd); u32 hfi1_read_cntrs(struct hfi1_devdata *dd, char **namep, u64 **cntrp); u32 hfi1_read_portcntrs(struct hfi1_pportdata *ppd, char **namep, u64 **cntrp); int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which); int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val); int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd, u16 jkey); int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt); int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt, u16 pkey); int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, struct hfi1_ctxtdata *ctxt); void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality); void hfi1_init_vnic_rsm(struct hfi1_devdata *dd); void hfi1_deinit_vnic_rsm(struct hfi1_devdata *dd); irqreturn_t general_interrupt(int irq, void *data); irqreturn_t sdma_interrupt(int irq, void *data); irqreturn_t receive_context_interrupt(int irq, void *data); irqreturn_t receive_context_thread(int irq, void *data); irqreturn_t receive_context_interrupt_napi(int irq, void *data); int set_intr_bits(struct hfi1_devdata *dd, u16 first, u16 last, bool set); void init_qsfp_int(struct hfi1_devdata *dd); void clear_all_interrupts(struct hfi1_devdata *dd); void remap_intr(struct hfi1_devdata *dd, int isrc, int msix_intr); void remap_sdma_interrupts(struct hfi1_devdata *dd, int engine, int msix_intr); void reset_interrupts(struct hfi1_devdata *dd); u8 hfi1_get_qp_map(struct hfi1_devdata *dd, u8 idx); void hfi1_init_aip_rsm(struct hfi1_devdata *dd); void hfi1_deinit_aip_rsm(struct hfi1_devdata *dd); /* * Interrupt source table. * * Each entry is an interrupt source "type". It is ordered by increasing * number. */ struct is_table { … }; #endif /* _CHIP_H */
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