linux/drivers/clk/ingenic/jz4760-cgu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * JZ4760 SoC CGU driver
 * Copyright 2018, Paul Cercueil <[email protected]>
 */

#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>

#include <linux/clk.h>

#include <dt-bindings/clock/ingenic,jz4760-cgu.h>

#include "cgu.h"
#include "pm.h"

#define MHZ …

/*
 * CPM registers offset address definition
 */
#define CGU_REG_CPCCR …
#define CGU_REG_LCR …
#define CGU_REG_CPPCR0 …
#define CGU_REG_CLKGR0 …
#define CGU_REG_OPCR …
#define CGU_REG_CLKGR1 …
#define CGU_REG_CPPCR1 …
#define CGU_REG_USBPCR …
#define CGU_REG_USBCDR …
#define CGU_REG_I2SCDR …
#define CGU_REG_LPCDR …
#define CGU_REG_MSCCDR …
#define CGU_REG_UHCCDR …
#define CGU_REG_SSICDR …
#define CGU_REG_CIMCDR …
#define CGU_REG_GPSCDR …
#define CGU_REG_PCMCDR …
#define CGU_REG_GPUCDR …

static const s8 pll_od_encoding[8] = …;

static const u8 jz4760_cgu_cpccr_div_table[] = …;

static const u8 jz4760_cgu_pll_half_div_table[] = …;

static void
jz4760_cgu_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
		       unsigned long rate, unsigned long parent_rate,
		       unsigned int *pm, unsigned int *pn, unsigned int *pod)
{ … }

static const struct ingenic_cgu_clk_info jz4760_cgu_clocks[] = …;

static void __init jz4760_cgu_init(struct device_node *np)
{ … }

/* We only probe via devicetree, no need for a platform driver */
CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-cgu", jz4760_cgu_init);

/* JZ4760B has some small differences, but we don't implement them. */
CLK_OF_DECLARE_DRIVER(jz4760b_cgu, "ingenic,jz4760b-cgu", jz4760_cgu_init);