#include <linux/bitfield.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "hfi.h"
#include "chip_registers.h"
#include "aspm.h"
int hfi1_pcie_init(struct hfi1_devdata *dd)
{ … }
void hfi1_pcie_cleanup(struct pci_dev *pdev)
{ … }
int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
{ … }
void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
{ … }
static u32 extract_speed(u16 linkstat)
{ … }
static void update_lbus_info(struct hfi1_devdata *dd)
{ … }
int pcie_speeds(struct hfi1_devdata *dd)
{ … }
int restore_pci_variables(struct hfi1_devdata *dd)
{ … }
int save_pci_variables(struct hfi1_devdata *dd)
{ … }
static int hfi1_pcie_caps;
module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444);
MODULE_PARM_DESC(…) …;
void tune_pcie_caps(struct hfi1_devdata *dd)
{ … }
static pci_ers_result_t
pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
{ … }
static pci_ers_result_t
pci_mmio_enabled(struct pci_dev *pdev)
{ … }
static pci_ers_result_t
pci_slot_reset(struct pci_dev *pdev)
{ … }
static void
pci_resume(struct pci_dev *pdev)
{ … }
const struct pci_error_handlers hfi1_pci_err_handler = …;
#define DL_STATUS_HFI0 …
#define DL_STATUS_HFI1 …
#define DL_STATUS_BOTH …
#define DL_ERR_NONE …
#define DL_ERR_SWAP_PARITY …
#define DL_ERR_DISABLED …
#define DL_ERR_SECURITY …
#define DL_ERR_SBUS …
#define DL_ERR_XFR_PARITY …
#define SBR_DELAY_US …
static uint pcie_target = …;
module_param(pcie_target, uint, S_IRUGO);
MODULE_PARM_DESC(…) …;
static uint pcie_force;
module_param(pcie_force, uint, S_IRUGO);
MODULE_PARM_DESC(…) …;
static uint pcie_retry = …;
module_param(pcie_retry, uint, S_IRUGO);
MODULE_PARM_DESC(…) …;
#define UNSET_PSET …
#define DEFAULT_DISCRETE_PSET …
#define DEFAULT_MCP_PSET …
static uint pcie_pset = …;
module_param(pcie_pset, uint, S_IRUGO);
MODULE_PARM_DESC(…) …;
static uint pcie_ctle = …;
module_param(pcie_ctle, uint, S_IRUGO);
MODULE_PARM_DESC(…) …;
#define PREC …
#define ATTN …
#define POST …
static const u8 discrete_preliminary_eq[11][3] = …;
static const u8 integrated_preliminary_eq[11][3] = …;
static const u8 discrete_ctle_tunings[11][4] = …;
static const u8 integrated_ctle_tunings[11][4] = …;
#define eq_value(pre, curr, post) …
static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
u8 div)
{ … }
static void pcie_post_steps(struct hfi1_devdata *dd)
{ … }
static int trigger_sbr(struct hfi1_devdata *dd)
{ … }
static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
u16 code, u16 data)
{ … }
static void arm_gasket_logic(struct hfi1_devdata *dd)
{ … }
#define LANE_BUNDLE_MASK …
#define LANE_BUNDLE_SHIFT …
#define LANE_DELAY_MASK …
#define LANE_DELAY_SHIFT …
#define MARGIN_OVERWRITE_ENABLE_SHIFT …
#define MARGIN_SHIFT …
#define MARGIN_G1_G2_OVERWRITE_MASK …
#define MARGIN_G1_G2_OVERWRITE_SHIFT …
#define MARGIN_GEN1_GEN2_MASK …
#define MARGIN_GEN1_GEN2_SHIFT …
static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
{ … }
int do_pcie_gen3_transition(struct hfi1_devdata *dd)
{ … }