linux/drivers/infiniband/hw/hfi1/pcie.c

// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/*
 * Copyright(c) 2015 - 2019 Intel Corporation.
 */

#include <linux/bitfield.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/vmalloc.h>
#include <linux/module.h>

#include "hfi.h"
#include "chip_registers.h"
#include "aspm.h"

/*
 * This file contains PCIe utility routines.
 */

/*
 * Do all the common PCIe setup and initialization.
 */
int hfi1_pcie_init(struct hfi1_devdata *dd)
{}

/*
 * Clean what was done in hfi1_pcie_init()
 */
void hfi1_pcie_cleanup(struct pci_dev *pdev)
{}

/*
 * Do remaining PCIe setup, once dd is allocated, and save away
 * fields required to re-initialize after a chip reset, or for
 * various other purposes
 */
int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
{}

/*
 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc.  Just prior
 * to releasing the dd memory.
 * Void because all of the core pcie cleanup functions are void.
 */
void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
{}

/* return the PCIe link speed from the given link status */
static u32 extract_speed(u16 linkstat)
{}

/* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
static void update_lbus_info(struct hfi1_devdata *dd)
{}

/*
 * Read in the current PCIe link width and speed.  Find if the link is
 * Gen3 capable.
 */
int pcie_speeds(struct hfi1_devdata *dd)
{}

/*
 * Restore command and BARs after a reset has wiped them out
 *
 * Returns 0 on success, otherwise a negative error value
 */
int restore_pci_variables(struct hfi1_devdata *dd)
{}

/*
 * Save BARs and command to rewrite after device reset
 *
 * Returns 0 on success, otherwise a negative error value
 */
int save_pci_variables(struct hfi1_devdata *dd)
{}

/*
 * BIOS may not set PCIe bus-utilization parameters for best performance.
 * Check and optionally adjust them to maximize our throughput.
 */
static int hfi1_pcie_caps;
module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444);
MODULE_PARM_DESC();

/**
 * tune_pcie_caps() - Code to adjust PCIe capabilities.
 * @dd: Valid device data structure
 *
 */
void tune_pcie_caps(struct hfi1_devdata *dd)
{}

/* End of PCIe capability tuning */

/*
 * From here through hfi1_pci_err_handler definition is invoked via
 * PCI error infrastructure, registered via pci
 */
static pci_ers_result_t
pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
{}

static pci_ers_result_t
pci_mmio_enabled(struct pci_dev *pdev)
{}

static pci_ers_result_t
pci_slot_reset(struct pci_dev *pdev)
{}

static void
pci_resume(struct pci_dev *pdev)
{}

const struct pci_error_handlers hfi1_pci_err_handler =;

/*============================================================================*/
/* PCIe Gen3 support */

/*
 * This code is separated out because it is expected to be removed in the
 * final shipping product.  If not, then it will be revisited and items
 * will be moved to more standard locations.
 */

/* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
#define DL_STATUS_HFI0
#define DL_STATUS_HFI1
#define DL_STATUS_BOTH

/* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
#define DL_ERR_NONE
#define DL_ERR_SWAP_PARITY
					/*   or response data */
#define DL_ERR_DISABLED
#define DL_ERR_SECURITY
#define DL_ERR_SBUS
#define DL_ERR_XFR_PARITY

/* gasket block secondary bus reset delay */
#define SBR_DELAY_US

static uint pcie_target =;
module_param(pcie_target, uint, S_IRUGO);
MODULE_PARM_DESC();

static uint pcie_force;
module_param(pcie_force, uint, S_IRUGO);
MODULE_PARM_DESC();

static uint pcie_retry =;
module_param(pcie_retry, uint, S_IRUGO);
MODULE_PARM_DESC();

#define UNSET_PSET
#define DEFAULT_DISCRETE_PSET
#define DEFAULT_MCP_PSET
static uint pcie_pset =;
module_param(pcie_pset, uint, S_IRUGO);
MODULE_PARM_DESC();

static uint pcie_ctle =; /* discrete on, integrated on */
module_param(pcie_ctle, uint, S_IRUGO);
MODULE_PARM_DESC();

/* equalization columns */
#define PREC
#define ATTN
#define POST

/* discrete silicon preliminary equalization values */
static const u8 discrete_preliminary_eq[11][3] =;

/* integrated silicon preliminary equalization values */
static const u8 integrated_preliminary_eq[11][3] =;

static const u8 discrete_ctle_tunings[11][4] =;

static const u8 integrated_ctle_tunings[11][4] =;

/* helper to format the value to write to hardware */
#define eq_value(pre, curr, post)

/*
 * Load the given EQ preset table into the PCIe hardware.
 */
static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
			 u8 div)
{}

/*
 * Steps to be done after the PCIe firmware is downloaded and
 * before the SBR for the Pcie Gen3.
 * The SBus resource is already being held.
 */
static void pcie_post_steps(struct hfi1_devdata *dd)
{}

/*
 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
 *
 * Based on pci_parent_bus_reset() which is not exported by the
 * kernel core.
 */
static int trigger_sbr(struct hfi1_devdata *dd)
{}

/*
 * Write the given gasket interrupt register.
 */
static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
				   u16 code, u16 data)
{}

/*
 * Tell the gasket logic how to react to the reset.
 */
static void arm_gasket_logic(struct hfi1_devdata *dd)
{}

/*
 * CCE_PCIE_CTRL long name helpers
 * We redefine these shorter macros to use in the code while leaving
 * chip_registers.h to be autogenerated from the hardware spec.
 */
#define LANE_BUNDLE_MASK
#define LANE_BUNDLE_SHIFT
#define LANE_DELAY_MASK
#define LANE_DELAY_SHIFT
#define MARGIN_OVERWRITE_ENABLE_SHIFT
#define MARGIN_SHIFT
#define MARGIN_G1_G2_OVERWRITE_MASK
#define MARGIN_G1_G2_OVERWRITE_SHIFT
#define MARGIN_GEN1_GEN2_MASK
#define MARGIN_GEN1_GEN2_SHIFT

 /*
  * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
  */
static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
{}

/*
 * Do all the steps needed to transition the PCIe link to Gen3 speed.
 */
int do_pcie_gen3_transition(struct hfi1_devdata *dd)
{}