// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* * Copyright(c) 2015, 2016 Intel Corporation. */ #include <linux/delay.h> #include <linux/pci.h> #include <linux/vmalloc.h> #include "hfi.h" /* for the given bus number, return the CSR for reading an i2c line */ static inline u32 i2c_in_csr(u32 bus_num) { … } /* for the given bus number, return the CSR for writing an i2c line */ static inline u32 i2c_oe_csr(u32 bus_num) { … } static void hfi1_setsda(void *data, int state) { … } static void hfi1_setscl(void *data, int state) { … } static int hfi1_getsda(void *data) { … } static int hfi1_getscl(void *data) { … } /* * Allocate and initialize the given i2c bus number. * Returns NULL on failure. */ static struct hfi1_i2c_bus *init_i2c_bus(struct hfi1_devdata *dd, struct hfi1_asic_data *ad, int num) { … } /* * Initialize i2c buses. * Return 0 on success, -errno on error. */ int set_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad) { ad->i2c_bus0 = init_i2c_bus(dd, ad, 0); ad->i2c_bus1 = init_i2c_bus(dd, ad, 1); if (!ad->i2c_bus0 || !ad->i2c_bus1) return -ENOMEM; return 0; }; static void clean_i2c_bus(struct hfi1_i2c_bus *bus) { … } void clean_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad) { … } static int i2c_bus_write(struct hfi1_devdata *dd, struct hfi1_i2c_bus *i2c, u8 slave_addr, int offset, int offset_size, u8 *data, u16 len) { … } static int i2c_bus_read(struct hfi1_devdata *dd, struct hfi1_i2c_bus *bus, u8 slave_addr, int offset, int offset_size, u8 *data, u16 len) { … } /* * Raw i2c write. No set-up or lock checking. * * Return 0 on success, -errno on error. */ static int __i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset, void *bp, int len) { … } /* * Caller must hold the i2c chain resource. * * Return number of bytes written, or -errno. */ int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset, void *bp, int len) { … } /* * Raw i2c read. No set-up or lock checking. * * Return 0 on success, -errno on error. */ static int __i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset, void *bp, int len) { … } /* * Caller must hold the i2c chain resource. * * Return number of bytes read, or -errno. */ int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset, void *bp, int len) { … } /* * Write page n, offset m of QSFP memory as defined by SFF 8636 * by writing @addr = ((256 * n) + m) * * Caller must hold the i2c chain resource. * * Return number of bytes written or -errno. */ int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, int len) { … } /* * Perform a stand-alone single QSFP write. Acquire the resource, do the * write, then release the resource. */ int one_qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, int len) { … } /* * Access page n, offset m of QSFP memory as defined by SFF 8636 * by reading @addr = ((256 * n) + m) * * Caller must hold the i2c chain resource. * * Return the number of bytes read or -errno. */ int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, int len) { … } /* * Perform a stand-alone single QSFP read. Acquire the resource, do the * read, then release the resource. */ int one_qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, int len) { … } /* * This function caches the QSFP memory range in 128 byte chunks. * As an example, the next byte after address 255 is byte 128 from * upper page 01H (if existing) rather than byte 0 from lower page 00H. * Access page n, offset m of QSFP memory as defined by SFF 8636 * in the cache by reading byte ((128 * n) + m) * The calls to qsfp_{read,write} in this function correctly handle the * address map difference between this mapping and the mapping implemented * by those functions * * The caller must be holding the QSFP i2c chain resource. */ int refresh_qsfp_cache(struct hfi1_pportdata *ppd, struct qsfp_data *cp) { … } const char * const hfi1_qsfp_devtech[16] = …; #define QSFP_DUMP_CHUNK … #define QSFP_DEFAULT_HDR_CNT … #define QSFP_PWR(pbyte) … #define QSFP_HIGH_PWR(pbyte) … /* For use with QSFP_HIGH_PWR macro */ #define QSFP_HIGH_PWR_UNUSED … /* * Takes power class byte [Page 00 Byte 129] in SFF 8636 * Returns power class as integer (1 through 7, per SFF 8636 rev 2.4) */ int get_qsfp_power_class(u8 power_byte) { … } int qsfp_mod_present(struct hfi1_pportdata *ppd) { … } /* * This function maps QSFP memory addresses in 128 byte chunks in the following * fashion per the CableInfo SMA query definition in the IBA 1.3 spec/OPA Gen 1 * spec * For addr 000-127, lower page 00h * For addr 128-255, upper page 00h * For addr 256-383, upper page 01h * For addr 384-511, upper page 02h * For addr 512-639, upper page 03h * * For addresses beyond this range, it returns the invalid range of data buffer * set to 0. * For upper pages that are optional, if they are not valid, returns the * particular range of bytes in the data buffer set to 0. */ int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr, u32 len, u8 *data) { … } static const char *pwr_codes[8] = …; int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len) { … }