linux/drivers/clk/ingenic/jz4770-cgu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * JZ4770 SoC CGU driver
 * Copyright 2018, Paul Cercueil <[email protected]>
 */

#include <linux/bitops.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>

#include <dt-bindings/clock/ingenic,jz4770-cgu.h>

#include "cgu.h"
#include "pm.h"

/*
 * CPM registers offset address definition
 */
#define CGU_REG_CPCCR …
#define CGU_REG_LCR …
#define CGU_REG_CPPCR0 …
#define CGU_REG_CLKGR0 …
#define CGU_REG_OPCR …
#define CGU_REG_CLKGR1 …
#define CGU_REG_CPPCR1 …
#define CGU_REG_USBPCR1 …
#define CGU_REG_USBCDR …
#define CGU_REG_I2SCDR …
#define CGU_REG_LPCDR …
#define CGU_REG_MSC0CDR …
#define CGU_REG_UHCCDR …
#define CGU_REG_SSICDR …
#define CGU_REG_CIMCDR …
#define CGU_REG_GPSCDR …
#define CGU_REG_PCMCDR …
#define CGU_REG_GPUCDR …
#define CGU_REG_MSC1CDR …
#define CGU_REG_MSC2CDR …
#define CGU_REG_BCHCDR …

/* bits within the OPCR register */
#define OPCR_SPENDH …

/* bits within the USBPCR1 register */
#define USBPCR1_UHC_POWER …

static struct ingenic_cgu *cgu;

static int jz4770_uhc_phy_enable(struct clk_hw *hw)
{ … }

static void jz4770_uhc_phy_disable(struct clk_hw *hw)
{ … }

static int jz4770_uhc_phy_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops jz4770_uhc_phy_ops = …;

static const s8 pll_od_encoding[8] = …;

static const u8 jz4770_cgu_cpccr_div_table[] = …;

static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = …;

static void __init jz4770_cgu_init(struct device_node *np)
{ … }

/* We only probe via devicetree, no need for a platform driver */
CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);