linux/include/dt-bindings/clock/ingenic,jz4780-cgu.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * This header provides clock numbers for the ingenic,jz4780-cgu DT binding.
 *
 * They are roughly ordered as:
 *   - external clocks
 *   - PLLs
 *   - muxes/dividers in the order they appear in the jz4780 programmers manual
 *   - gates in order of their bit in the CLKGR* registers
 */

#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__

#define JZ4780_CLK_EXCLK
#define JZ4780_CLK_RTCLK
#define JZ4780_CLK_APLL
#define JZ4780_CLK_MPLL
#define JZ4780_CLK_EPLL
#define JZ4780_CLK_VPLL
#define JZ4780_CLK_OTGPHY
#define JZ4780_CLK_SCLKA
#define JZ4780_CLK_CPUMUX
#define JZ4780_CLK_CPU
#define JZ4780_CLK_L2CACHE
#define JZ4780_CLK_AHB0
#define JZ4780_CLK_AHB2PMUX
#define JZ4780_CLK_AHB2
#define JZ4780_CLK_PCLK
#define JZ4780_CLK_DDR
#define JZ4780_CLK_VPU
#define JZ4780_CLK_I2SPLL
#define JZ4780_CLK_I2S
#define JZ4780_CLK_LCD0PIXCLK
#define JZ4780_CLK_LCD1PIXCLK
#define JZ4780_CLK_MSCMUX
#define JZ4780_CLK_MSC0
#define JZ4780_CLK_MSC1
#define JZ4780_CLK_MSC2
#define JZ4780_CLK_UHC
#define JZ4780_CLK_SSIPLL
#define JZ4780_CLK_SSI
#define JZ4780_CLK_CIMMCLK
#define JZ4780_CLK_PCMPLL
#define JZ4780_CLK_PCM
#define JZ4780_CLK_GPU
#define JZ4780_CLK_HDMI
#define JZ4780_CLK_BCH
#define JZ4780_CLK_NEMC
#define JZ4780_CLK_OTG0
#define JZ4780_CLK_SSI0
#define JZ4780_CLK_SMB0
#define JZ4780_CLK_SMB1
#define JZ4780_CLK_SCC
#define JZ4780_CLK_AIC
#define JZ4780_CLK_TSSI0
#define JZ4780_CLK_OWI
#define JZ4780_CLK_KBC
#define JZ4780_CLK_SADC
#define JZ4780_CLK_UART0
#define JZ4780_CLK_UART1
#define JZ4780_CLK_UART2
#define JZ4780_CLK_UART3
#define JZ4780_CLK_SSI1
#define JZ4780_CLK_SSI2
#define JZ4780_CLK_PDMA
#define JZ4780_CLK_GPS
#define JZ4780_CLK_MAC
#define JZ4780_CLK_SMB2
#define JZ4780_CLK_CIM
#define JZ4780_CLK_LCD
#define JZ4780_CLK_TVE
#define JZ4780_CLK_IPU
#define JZ4780_CLK_DDR0
#define JZ4780_CLK_DDR1
#define JZ4780_CLK_SMB3
#define JZ4780_CLK_TSSI1
#define JZ4780_CLK_COMPRESS
#define JZ4780_CLK_AIC1
#define JZ4780_CLK_GPVLC
#define JZ4780_CLK_OTG1
#define JZ4780_CLK_UART4
#define JZ4780_CLK_AHBMON
#define JZ4780_CLK_SMB4
#define JZ4780_CLK_DES
#define JZ4780_CLK_X2D
#define JZ4780_CLK_CORE1
#define JZ4780_CLK_EXCLK_DIV512
#define JZ4780_CLK_RTC

#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */