// SPDX-License-Identifier: GPL-2.0-or-later /* * Ingenic JZ4780 SoC CGU driver * * Copyright (c) 2013-2015 Imagination Technologies * Author: Paul Burton <[email protected]> * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/of.h> #include <dt-bindings/clock/ingenic,jz4780-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CLOCKCONTROL … #define CGU_REG_LCR … #define CGU_REG_APLL … #define CGU_REG_MPLL … #define CGU_REG_EPLL … #define CGU_REG_VPLL … #define CGU_REG_CLKGR0 … #define CGU_REG_OPCR … #define CGU_REG_CLKGR1 … #define CGU_REG_DDRCDR … #define CGU_REG_VPUCDR … #define CGU_REG_USBPCR … #define CGU_REG_USBRDT … #define CGU_REG_USBVBFIL … #define CGU_REG_USBPCR1 … #define CGU_REG_LP0CDR … #define CGU_REG_I2SCDR … #define CGU_REG_LP1CDR … #define CGU_REG_MSC0CDR … #define CGU_REG_UHCCDR … #define CGU_REG_SSICDR … #define CGU_REG_CIMCDR … #define CGU_REG_PCMCDR … #define CGU_REG_GPUCDR … #define CGU_REG_HDMICDR … #define CGU_REG_MSC1CDR … #define CGU_REG_MSC2CDR … #define CGU_REG_BCHCDR … #define CGU_REG_CLOCKSTATUS … /* bits within the OPCR register */ #define OPCR_SPENDN0 … #define OPCR_SPENDN1 … /* bits within the USBPCR register */ #define USBPCR_USB_MODE … #define USBPCR_IDPULLUP_MASK … #define USBPCR_COMMONONN … #define USBPCR_VBUSVLDEXT … #define USBPCR_VBUSVLDEXTSEL … #define USBPCR_POR … #define USBPCR_SIDDQ … #define USBPCR_OTG_DISABLE … #define USBPCR_COMPDISTUNE_MASK … #define USBPCR_OTGTUNE_MASK … #define USBPCR_SQRXTUNE_MASK … #define USBPCR_TXFSLSTUNE_MASK … #define USBPCR_TXPREEMPHTUNE … #define USBPCR_TXHSXVTUNE_MASK … #define USBPCR_TXVREFTUNE_MASK … /* bits within the USBPCR1 register */ #define USBPCR1_REFCLKSEL_SHIFT … #define USBPCR1_REFCLKSEL_MASK … #define USBPCR1_REFCLKSEL_CORE … #define USBPCR1_REFCLKDIV_SHIFT … #define USBPCR1_REFCLKDIV_MASK … #define USBPCR1_REFCLKDIV_19_2 … #define USBPCR1_REFCLKDIV_48 … #define USBPCR1_REFCLKDIV_24 … #define USBPCR1_REFCLKDIV_12 … #define USBPCR1_USB_SEL … #define USBPCR1_WORD_IF0 … #define USBPCR1_WORD_IF1 … /* bits within the USBRDT register */ #define USBRDT_VBFIL_LD_EN … #define USBRDT_USBRDT_MASK … /* bits within the USBVBFIL register */ #define USBVBFIL_IDDIGFIL_SHIFT … #define USBVBFIL_IDDIGFIL_MASK … #define USBVBFIL_USBVBFIL_MASK … /* bits within the LCR register */ #define LCR_PD_SCPU … #define LCR_SCPUS … /* bits within the CLKGR1 register */ #define CLKGR1_CORE1 … static struct ingenic_cgu *cgu; static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long *parent_rate) { … } static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { … } static int jz4780_otg_phy_enable(struct clk_hw *hw) { … } static void jz4780_otg_phy_disable(struct clk_hw *hw) { … } static int jz4780_otg_phy_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops jz4780_otg_phy_ops = …; static int jz4780_core1_enable(struct clk_hw *hw) { … } static const struct clk_ops jz4780_core1_ops = …; static const s8 pll_od_encoding[16] = …; static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = …; static void __init jz4780_cgu_init(struct device_node *np) { … } CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
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