/* * Copyright (c) 2016-2017 Hisilicon Limited. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef _HNS_ROCE_HW_V2_H #define _HNS_ROCE_HW_V2_H #include <linux/bitops.h> #define HNS_ROCE_V2_MAX_RC_INL_INN_SZ … #define HNS_ROCE_V2_MTT_ENTRY_SZ … #define HNS_ROCE_V2_AEQE_VEC_NUM … #define HNS_ROCE_V2_ABNORMAL_VEC_NUM … #define HNS_ROCE_V2_MAX_SRQWQE_SEGS … #define HNS_ROCE_V2_MAX_IDX_SEGS … #define HNS_ROCE_V2_MAX_XRCD_NUM … #define HNS_ROCE_V2_QP_ACK_TIMEOUT_OFS_HIP08 … #define HNS_ROCE_V3_SCCC_SZ … #define HNS_ROCE_V3_GMV_ENTRY_SZ … #define HNS_ROCE_V2_EXT_LLM_ENTRY_SZ … #define HNS_ROCE_V2_EXT_LLM_MAX_DEPTH … #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ … #define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ … #define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED … #define HNS_ROCE_V2_MAX_INNER_MTPT_NUM … #define HNS_ROCE_INVALID_LKEY … #define HNS_ROCE_INVALID_SGE_LENGTH … #define HNS_ROCE_CMQ_TX_TIMEOUT … #define HNS_ROCE_V2_RSV_QPS … #define HNS_ROCE_V2_HW_RST_TIMEOUT … #define HNS_ROCE_V2_HW_RST_UNINT_DELAY … #define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT … #define HNS_ROCE_CONTEXT_HOP_NUM … #define HNS_ROCE_SCCC_HOP_NUM … #define HNS_ROCE_MTT_HOP_NUM … #define HNS_ROCE_CQE_HOP_NUM … #define HNS_ROCE_SRQWQE_HOP_NUM … #define HNS_ROCE_PBL_HOP_NUM … #define HNS_ROCE_IDX_HOP_NUM … #define HNS_ROCE_SQWQE_HOP_NUM … #define HNS_ROCE_EXT_SGE_HOP_NUM … #define HNS_ROCE_RQWQE_HOP_NUM … #define HNS_ROCE_V2_EQE_HOP_NUM … #define HNS_ROCE_V3_EQE_HOP_NUM … #define HNS_ROCE_BA_PG_SZ_SUPPORTED_256K … #define HNS_ROCE_BA_PG_SZ_SUPPORTED_16K … #define HNS_ROCE_V2_GID_INDEX_NUM … #define HNS_ROCE_V2_TABLE_CHUNK_SIZE … enum { … }; #define HNS_ROCE_CMQ_DESC_NUM_S … #define HNS_ROCE_CMQ_SCC_CLR_DONE_CNT … #define HNS_ROCE_CONG_SIZE … #define check_whether_last_step(hop_num, step_idx) … #define HNS_ICL_SWITCH_CMD_ROCEE_SEL_SHIFT … #define HNS_ICL_SWITCH_CMD_ROCEE_SEL … #define CMD_CSQ_DESC_NUM … #define CMD_CRQ_DESC_NUM … /* Free mr used parameters */ #define HNS_ROCE_FREE_MR_USED_CQE_NUM … #define HNS_ROCE_FREE_MR_USED_QP_NUM … #define HNS_ROCE_FREE_MR_USED_PSN … #define HNS_ROCE_FREE_MR_USED_QP_RETRY_CNT … #define HNS_ROCE_FREE_MR_USED_QP_TIMEOUT … #define HNS_ROCE_FREE_MR_USED_SQWQE_NUM … #define HNS_ROCE_FREE_MR_USED_SQSGE_NUM … #define HNS_ROCE_FREE_MR_USED_RQWQE_NUM … #define HNS_ROCE_FREE_MR_USED_RQSGE_NUM … #define HNS_ROCE_V2_FREE_MR_TIMEOUT … enum { … }; enum { … }; #define V2_CQ_DB_REQ_NOT_SOL … #define V2_CQ_DB_REQ_NOT … #define V2_CQ_STATE_VALID … #define V2_QKEY_VAL … #define GID_LEN_V2 … enum { … }; enum { … }; enum { … }; enum { … }; /* CMQ command */ enum hns_roce_opcode_type { … }; #define HNS_ROCE_OPC_POST_MB_TIMEOUT … struct hns_roce_cmdq_tx_timeout_map { … }; enum { … }; enum hns_roce_cmd_return_status { … }; struct hns_roce_cmd_errcode { … }; enum hns_roce_sgid_type { … }; struct hns_roce_v2_cq_context { … }; #define CQC_CQE_BA_L_S … #define CQC_CQE_BA_H_S … #define CQC_CQE_DB_RECORD_ADDR_H_S … #define HNS_ROCE_V2_CQ_DEFAULT_BURST_NUM … #define HNS_ROCE_V2_CQ_DEFAULT_INTERVAL … #define CQC_FIELD_LOC(h, l) … #define CQC_CQ_ST … #define CQC_POLL … #define CQC_SE … #define CQC_OVER_IGNORE … #define CQC_ARM_ST … #define CQC_SHIFT … #define CQC_CMD_SN … #define CQC_CEQN … #define CQC_CQN … #define CQC_POE_EN … #define CQC_POE_NUM … #define CQC_CQE_SIZE … #define CQC_CQ_CNT_MODE … #define CQC_STASH … #define CQC_CQE_CUR_BLK_ADDR_L … #define CQC_CQE_CUR_BLK_ADDR_H … #define CQC_POE_QID … #define CQC_CQE_HOP_NUM … #define CQC_CQE_NEX_BLK_ADDR_L … #define CQC_CQE_NEX_BLK_ADDR_H … #define CQC_CQE_BAR_PG_SZ … #define CQC_CQE_BUF_PG_SZ … #define CQC_CQ_PRODUCER_IDX … #define CQC_CQ_CONSUMER_IDX … #define CQC_CQE_BA_L … #define CQC_CQE_BA_H … #define CQC_POE_QID_H_0 … #define CQC_DB_RECORD_EN … #define CQC_CQE_DB_RECORD_ADDR_L … #define CQC_CQE_DB_RECORD_ADDR_H … #define CQC_CQE_CNT … #define CQC_CQ_MAX_CNT … #define CQC_CQ_PERIOD … #define CQC_CQE_REPORT_TIMER … #define CQC_WR_CQE_IDX … #define CQC_SE_CQE_IDX … #define CQC_POE_QID_H_1 … struct hns_roce_srq_context { … }; #define SRQC_FIELD_LOC(h, l) … #define SRQC_SRQ_ST … #define SRQC_WQE_HOP_NUM … #define SRQC_SHIFT … #define SRQC_SRQN … #define SRQC_LIMIT_WL … #define SRQC_RSV0 … #define SRQC_XRCD … #define SRQC_RSV1 … #define SRQC_PRODUCER_IDX … #define SRQC_CONSUMER_IDX … #define SRQC_WQE_BT_BA_L … #define SRQC_WQE_BT_BA_H … #define SRQC_RSV2 … #define SRQC_SRQ_TYPE … #define SRQC_PD … #define SRQC_RQWS … #define SRQC_RSV3 … #define SRQC_IDX_BT_BA_L … #define SRQC_IDX_BT_BA_H … #define SRQC_RSV4 … #define SRQC_IDX_CUR_BLK_ADDR_L … #define SRQC_IDX_CUR_BLK_ADDR_H … #define SRQC_RSV5 … #define SRQC_IDX_HOP_NUM … #define SRQC_IDX_BA_PG_SZ … #define SRQC_IDX_BUF_PG_SZ … #define SRQC_IDX_NXT_BLK_ADDR_L … #define SRQC_IDX_NXT_BLK_ADDR_H … #define SRQC_RSV6 … #define SRQC_XRC_CQN … #define SRQC_WQE_BA_PG_SZ … #define SRQC_WQE_BUF_PG_SZ … #define SRQC_DB_RECORD_EN … #define SRQC_DB_RECORD_ADDR_L … #define SRQC_DB_RECORD_ADDR_H … enum { … }; enum hns_roce_v2_qp_state { … }; struct hns_roce_v2_qp_context_ex { … }; struct hns_roce_v2_qp_context { … }; #define QPC_TRRL_BA_L_S … #define QPC_TRRL_BA_M_S … #define QPC_TRRL_BA_H_S … #define QPC_IRRL_BA_L_S … #define QPC_IRRL_BA_H_S … #define QPC_FIELD_LOC(h, l) … #define QPC_TST … #define QPC_SGE_SHIFT … #define QPC_CNP_TIMER … #define QPC_WQE_SGE_BA_L … #define QPC_WQE_SGE_BA_H … #define QPC_SQ_HOP_NUM … #define QPC_CIRE_EN … #define QPC_WQE_SGE_BA_PG_SZ … #define QPC_WQE_SGE_BUF_PG_SZ … #define QPC_PD … #define QPC_RQ_HOP_NUM … #define QPC_SGE_HOP_NUM … #define QPC_RQWS … #define QPC_SQ_SHIFT … #define QPC_RQ_SHIFT … #define QPC_GMV_IDX … #define QPC_HOPLIMIT … #define QPC_TC … #define QPC_VLAN_ID … #define QPC_MTU … #define QPC_FL … #define QPC_SL … #define QPC_CNP_TX_FLAG … #define QPC_CE_FLAG … #define QPC_LBI … #define QPC_AT … #define QPC_DGID … #define QPC_DMAC_L … #define QPC_DMAC_H … #define QPC_UDPSPN … #define QPC_DQPN … #define QPC_SQ_TX_ERR … #define QPC_SQ_RX_ERR … #define QPC_RQ_TX_ERR … #define QPC_RQ_RX_ERR … #define QPC_LP_PKTN_INI … #define QPC_CONG_ALGO_TMPL_ID … #define QPC_SCC_TOKEN … #define QPC_SQ_DB_DOING … #define QPC_RQ_DB_DOING … #define QPC_QP_ST … #define QPC_QKEY_XRCD … #define QPC_RQ_RECORD_EN … #define QPC_RQ_DB_RECORD_ADDR_L … #define QPC_RQ_DB_RECORD_ADDR_H … #define QPC_SRQN … #define QPC_SRQ_EN … #define QPC_RRE … #define QPC_RWE … #define QPC_ATE … #define QPC_RQIE … #define QPC_EXT_ATE … #define QPC_RQ_VLAN_EN … #define QPC_RQ_RTY_TX_ERR … #define QPC_RX_CQN … #define QPC_XRC_QP_TYPE … #define QPC_CQEIE … #define QPC_CQEIS … #define QPC_MIN_RNR_TIME … #define QPC_RQ_PRODUCER_IDX … #define QPC_RQ_CONSUMER_IDX … #define QPC_RQ_CUR_BLK_ADDR_L … #define QPC_RQ_CUR_BLK_ADDR_H … #define QPC_SRQ_INFO … #define QPC_RX_REQ_MSN … #define QPC_REDUCE_CODE … #define QPC_RX_XRC_PKT_CQE_FLG … #define QPC_RQ_NXT_BLK_ADDR_L … #define QPC_RQ_NXT_BLK_ADDR_H … #define QPC_REDUCE_EN … #define QPC_FLUSH_EN … #define QPC_AW_EN … #define QPC_WN_EN … #define QPC_RQ_CUR_WQE_SGE_NUM … #define QPC_INV_CREDIT … #define QPC_LAST_WRITE_TYPE … #define QPC_RX_REQ_PSN_ERR … #define QPC_RX_REQ_LAST_OPTYPE … #define QPC_RX_REQ_RNR … #define QPC_RX_REQ_EPSN … #define QPC_RQ_RNR_TIMER … #define QPC_RX_MSG_LEN … #define QPC_RX_RKEY_PKT_INFO … #define QPC_RX_VA … #define QPC_TRRL_HEAD_MAX … #define QPC_TRRL_TAIL_MAX … #define QPC_TRRL_BA_L … #define QPC_TRRL_BA_M … #define QPC_TRRL_BA_H … #define QPC_RR_MAX … #define QPC_RQ_RTY_WAIT_DO … #define QPC_RAQ_TRRL_HEAD … #define QPC_RAQ_TRRL_TAIL … #define QPC_RAQ_RTY_INI_PSN … #define QPC_CIRE_SLV_RQ_EN … #define QPC_RAQ_CREDIT … #define QPC_RQ_DB_IN_EXT … #define QPC_RESP_RTY_FLG … #define QPC_RAQ_MSN … #define QPC_RAQ_SYNDROME … #define QPC_RAQ_PSN … #define QPC_RAQ_TRRL_RTY_HEAD … #define QPC_RAQ_USE_PKTN … #define QPC_RQ_SCC_TOKEN … #define QPC_RVD10 … #define QPC_SQ_PRODUCER_IDX … #define QPC_SQ_CONSUMER_IDX … #define QPC_SQ_CUR_BLK_ADDR_L … #define QPC_SQ_CUR_BLK_ADDR_H … #define QPC_MSG_RTY_LP_FLG … #define QPC_SQ_INVLD_FLG … #define QPC_LP_SGEN_INI … #define QPC_SQ_VLAN_EN … #define QPC_POLL_DB_WAIT_DO … #define QPC_SCC_TOKEN_FORBID_SQ_DEQ … #define QPC_WAIT_ACK_TIMEOUT … #define QPC_IRRL_IDX_LSB … #define QPC_ACK_REQ_FREQ … #define QPC_MSG_RNR_FLG … #define QPC_FRE … #define QPC_SQ_CUR_PSN … #define QPC_MSG_USE_PKTN … #define QPC_IRRL_HEAD_PRE … #define QPC_SQ_CUR_SGE_BLK_ADDR_L … #define QPC_SQ_CUR_SGE_BLK_ADDR_H … #define QPC_IRRL_IDX_MSB … #define QPC_CUR_SGE_OFFSET … #define QPC_CUR_SGE_IDX … #define QPC_EXT_SGE_NUM_LEFT … #define QPC_OWNER_MODE … #define QPC_CIRE_SLV_SQ_EN … #define QPC_CIRE_DOING … #define QPC_CIRE_RESULT … #define QPC_OWNER_DB_WAIT_DO … #define QPC_SQ_WQE_INVLD … #define QPC_DCA_MODE … #define QPC_RTY_OWNER_NOCHK … #define QPC_V2_IRRL_HEAD … #define QPC_SQ_MAX_PSN … #define QPC_SQ_MAX_IDX … #define QPC_LCL_OPERATED_CNT … #define QPC_IRRL_BA_L … #define QPC_IRRL_BA_H … #define QPC_PKT_RNR_FLG … #define QPC_PKT_RTY_FLG … #define QPC_RMT_E2E … #define QPC_SR_MAX … #define QPC_LSN … #define QPC_RETRY_NUM_INIT … #define QPC_CHECK_FLG … #define QPC_RETRY_CNT … #define QPC_SQ_TIMER … #define QPC_RETRY_MSG_MSN … #define QPC_RETRY_MSG_PSN_L … #define QPC_RETRY_MSG_PSN_H … #define QPC_RETRY_MSG_FPKT_PSN … #define QPC_RX_SQ_CUR_BLK_ADDR_L … #define QPC_RX_SQ_CUR_BLK_ADDR_H … #define QPC_IRRL_SGE_IDX … #define QPC_LSAN_EN … #define QPC_SO_LP_VLD … #define QPC_FENCE_LP_VLD … #define QPC_IRRL_LP_VLD … #define QPC_IRRL_CUR_SGE_OFFSET … #define QPC_IRRL_TAIL_REAL … #define QPC_IRRL_TAIL_RD … #define QPC_RX_ACK_MSN … #define QPC_RX_ACK_EPSN … #define QPC_RNR_NUM_INIT … #define QPC_RNR_CNT … #define QPC_LCL_OP_FLG … #define QPC_IRRL_RD_FLG … #define QPC_IRRL_PSN … #define QPC_ACK_PSN_ERR … #define QPC_ACK_LAST_OPTYPE … #define QPC_IRRL_PSN_VLD … #define QPC_RNR_RETRY_FLAG … #define QPC_SQ_RTY_TX_ERR … #define QPC_LAST_IND … #define QPC_CQ_ERR_IND … #define QPC_TX_CQN … #define QPC_SIG_TYPE … #define QPC_ERR_TYPE … #define QPC_RQ_CQE_IDX … #define QPC_SQ_FLUSH_IDX … #define RETRY_MSG_PSN_SHIFT … #define QPCEX_FIELD_LOC(h, l) … #define QPCEX_CONG_ALG_SEL … #define QPCEX_CONG_ALG_SUB_SEL … #define QPCEX_DIP_CTX_IDX_VLD … #define QPCEX_DIP_CTX_IDX … #define QPCEX_SQ_RQ_NOT_FORBID_EN … #define QPCEX_STASH … #define SCC_CONTEXT_SIZE … struct hns_roce_v2_scc_context { … }; #define V2_QP_RWE_S … #define V2_QP_RRE_S … #define V2_QP_ATE_S … struct hns_roce_v2_cqe { … }; #define CQE_FIELD_LOC(h, l) … #define CQE_OPCODE … #define CQE_RQ_INLINE … #define CQE_S_R … #define CQE_OWNER … #define CQE_STATUS … #define CQE_WQE_IDX … #define CQE_RKEY_IMMTDATA … #define CQE_XRC_SRQN … #define CQE_RSV0 … #define CQE_LCL_QPN … #define CQE_SUB_STATUS … #define CQE_BYTE_CNT … #define CQE_SMAC … #define CQE_PORT_TYPE … #define CQE_VID … #define CQE_VID_VLD … #define CQE_RSV2 … #define CQE_RMT_QPN … #define CQE_SL … #define CQE_PORTN … #define CQE_GRH … #define CQE_LPK … #define CQE_RSV3 … struct hns_roce_v2_mpt_entry { … }; #define MPT_PBL_BUF_ADDR_S … #define MPT_PBL_BA_ADDR_S … #define MPT_FIELD_LOC(h, l) … #define MPT_ST … #define MPT_PBL_HOP_NUM … #define MPT_PBL_BA_PG_SZ … #define MPT_PD … #define MPT_RA_EN … #define MPT_R_INV_EN … #define MPT_L_INV_EN … #define MPT_BIND_EN … #define MPT_ATOMIC_EN … #define MPT_RR_EN … #define MPT_RW_EN … #define MPT_LW_EN … #define MPT_MW_CNT … #define MPT_FRE … #define MPT_PA … #define MPT_ZBVA … #define MPT_SHARE … #define MPT_MR_MW … #define MPT_BPD … #define MPT_BQP … #define MPT_INNER_PA_VLD … #define MPT_MW_BIND_QPN … #define MPT_BOUND_LKEY … #define MPT_LEN_L … #define MPT_LEN_H … #define MPT_LKEY … #define MPT_VA … #define MPT_PBL_SIZE … #define MPT_PBL_BA_L … #define MPT_PBL_BA_H … #define MPT_BLK_MODE … #define MPT_RSV0 … #define MPT_PA0_L … #define MPT_PA0_H … #define MPT_BOUND_VA … #define MPT_PA1_L … #define MPT_PA1_H … #define MPT_PERSIST_EN … #define MPT_RSV2 … #define MPT_PBL_BUF_PG_SZ … #define V2_MPT_BYTE_4_MPT_ST_S … #define V2_MPT_BYTE_4_MPT_ST_M … #define V2_MPT_BYTE_4_PBL_HOP_NUM_S … #define V2_MPT_BYTE_4_PBL_HOP_NUM_M … #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_S … #define V2_MPT_BYTE_4_PBL_BA_PG_SZ_M … #define V2_MPT_BYTE_4_PD_S … #define V2_MPT_BYTE_4_PD_M … #define V2_MPT_BYTE_8_RA_EN_S … #define V2_MPT_BYTE_8_R_INV_EN_S … #define V2_MPT_BYTE_8_L_INV_EN_S … #define V2_MPT_BYTE_8_BIND_EN_S … #define V2_MPT_BYTE_8_ATOMIC_EN_S … #define V2_MPT_BYTE_8_RR_EN_S … #define V2_MPT_BYTE_8_RW_EN_S … #define V2_MPT_BYTE_8_LW_EN_S … #define V2_MPT_BYTE_8_MW_CNT_S … #define V2_MPT_BYTE_8_MW_CNT_M … #define V2_MPT_BYTE_12_FRE_S … #define V2_MPT_BYTE_12_PA_S … #define V2_MPT_BYTE_12_MR_MW_S … #define V2_MPT_BYTE_12_BPD_S … #define V2_MPT_BYTE_12_BQP_S … #define V2_MPT_BYTE_12_INNER_PA_VLD_S … #define V2_MPT_BYTE_12_MW_BIND_QPN_S … #define V2_MPT_BYTE_12_MW_BIND_QPN_M … #define V2_MPT_BYTE_48_PBL_BA_H_S … #define V2_MPT_BYTE_48_PBL_BA_H_M … #define V2_MPT_BYTE_48_BLK_MODE_S … #define V2_MPT_BYTE_56_PA0_H_S … #define V2_MPT_BYTE_56_PA0_H_M … #define V2_MPT_BYTE_64_PA1_H_S … #define V2_MPT_BYTE_64_PA1_H_M … #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S … #define V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M … struct hns_roce_v2_db { … }; #define DB_FIELD_LOC(h, l) … #define DB_TAG … #define DB_CMD … #define DB_FLAG … #define DB_PI … #define DB_SL … #define DB_CQ_CI … #define DB_CQ_NOTIFY … #define DB_CQ_CMD_SN … #define EQ_DB_TAG … #define EQ_DB_CMD … #define EQ_DB_CI … #define V2_DB_PRODUCER_IDX_S … #define V2_DB_PRODUCER_IDX_M … #define V2_CQ_DB_CONS_IDX_S … #define V2_CQ_DB_CONS_IDX_M … struct hns_roce_v2_ud_send_wqe { … }; #define UD_SEND_WQE_FIELD_LOC(h, l) … #define UD_SEND_WQE_OPCODE … #define UD_SEND_WQE_OWNER … #define UD_SEND_WQE_CQE … #define UD_SEND_WQE_SE … #define UD_SEND_WQE_PD … #define UD_SEND_WQE_SGE_NUM … #define UD_SEND_WQE_MSG_START_SGE_IDX … #define UD_SEND_WQE_UDPSPN … #define UD_SEND_WQE_DQPN … #define UD_SEND_WQE_VLAN … #define UD_SEND_WQE_HOPLIMIT … #define UD_SEND_WQE_TCLASS … #define UD_SEND_WQE_FLOW_LABEL … #define UD_SEND_WQE_SL … #define UD_SEND_WQE_VLAN_EN … #define UD_SEND_WQE_LBI … struct hns_roce_v2_rc_send_wqe { … }; #define RC_SEND_WQE_FIELD_LOC(h, l) … #define RC_SEND_WQE_OPCODE … #define RC_SEND_WQE_DB_SL_L … #define RC_SEND_WQE_DB_SL_H … #define RC_SEND_WQE_OWNER … #define RC_SEND_WQE_CQE … #define RC_SEND_WQE_FENCE … #define RC_SEND_WQE_SE … #define RC_SEND_WQE_INLINE … #define RC_SEND_WQE_WQE_INDEX … #define RC_SEND_WQE_FLAG … #define RC_SEND_WQE_XRC_SRQN … #define RC_SEND_WQE_SGE_NUM … #define RC_SEND_WQE_MSG_START_SGE_IDX … #define RC_SEND_WQE_INL_TYPE … struct hns_roce_wqe_frmr_seg { … }; #define FRMR_WQE_FIELD_LOC(h, l) … #define FRMR_PBL_SIZE … #define FRMR_BLOCK_SIZE … #define FRMR_PBL_BUF_PG_SZ … #define FRMR_BLK_MODE … #define FRMR_ZBVA … #define FRMR_BIND_EN … #define FRMR_ATOMIC … #define FRMR_RR … #define FRMR_RW … #define FRMR_LW … struct hns_roce_v2_wqe_data_seg { … }; struct hns_roce_query_version { … }; struct hns_roce_query_fw_info { … }; struct hns_roce_func_clear { … }; #define FUNC_CLEAR_FIELD_LOC(h, l) … #define FUNC_CLEAR_RST_FUN_DONE … /* Each physical function manages up to 248 virtual functions, it takes up to * 100ms for each function to execute clear. If an abnormal reset occurs, it is * executed twice at most, so it takes up to 249 * 2 * 100ms. */ #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS … #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL … #define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT … #define CFG_LLM_A_BA_L … #define CFG_LLM_A_BA_H … #define CFG_LLM_A_DEPTH … #define CFG_LLM_A_PGSZ … #define CFG_LLM_A_INIT_EN … #define CFG_LLM_A_HEAD_BA_L … #define CFG_LLM_A_HEAD_BA_H … #define CFG_LLM_A_HEAD_NXTPTR … #define CFG_LLM_A_HEAD_PTR … #define CFG_LLM_B_TAIL_BA_L … #define CFG_LLM_B_TAIL_BA_H … #define CFG_LLM_B_TAIL_PTR … /* Fields of HNS_ROCE_OPC_CFG_GLOBAL_PARAM */ #define CFG_GLOBAL_PARAM_1US_CYCLES … #define CFG_GLOBAL_PARAM_UDP_PORT … /* * Fields of HNS_ROCE_OPC_QUERY_PF_RES, HNS_ROCE_OPC_QUERY_VF_RES * and HNS_ROCE_OPC_ALLOC_VF_RES */ #define FUNC_RES_A_VF_ID … #define FUNC_RES_A_QPC_BT_IDX … #define FUNC_RES_A_QPC_BT_NUM … #define FUNC_RES_A_SRQC_BT_IDX … #define FUNC_RES_A_SRQC_BT_NUM … #define FUNC_RES_A_CQC_BT_IDX … #define FUNC_RES_A_CQC_BT_NUM … #define FUNC_RES_A_MPT_BT_IDX … #define FUNC_RES_A_MPT_BT_NUM … #define FUNC_RES_A_EQC_BT_IDX … #define FUNC_RES_A_EQC_BT_NUM … #define FUNC_RES_B_SMAC_IDX … #define FUNC_RES_B_SMAC_NUM … #define FUNC_RES_B_SGID_IDX … #define FUNC_RES_B_SGID_NUM … #define FUNC_RES_B_QID_IDX … #define FUNC_RES_B_QID_NUM … #define FUNC_RES_V_QID_NUM … #define FUNC_RES_B_SCCC_BT_IDX … #define FUNC_RES_B_SCCC_BT_NUM … #define FUNC_RES_B_GMV_BT_IDX … #define FUNC_RES_B_GMV_BT_NUM … #define FUNC_RES_V_GMV_BT_NUM … /* Fields of HNS_ROCE_OPC_QUERY_PF_TIMER_RES */ #define PF_TIMER_RES_QPC_ITEM_IDX … #define PF_TIMER_RES_QPC_ITEM_NUM … #define PF_TIMER_RES_CQC_ITEM_IDX … #define PF_TIMER_RES_CQC_ITEM_NUM … struct hns_roce_vf_switch { … }; #define VF_SWITCH_FIELD_LOC(h, l) … #define VF_SWITCH_VF_ID … #define VF_SWITCH_ALW_LPBK … #define VF_SWITCH_ALW_LCL_LPBK … #define VF_SWITCH_ALW_DST_OVRD … struct hns_roce_post_mbox { … }; struct hns_roce_mbox_status { … }; #define HNS_ROCE_V2_GO_BIT_TIMEOUT_MSECS … #define MB_ST_HW_RUN_M … #define MB_ST_COMPLETE_M … #define MB_ST_COMPLETE_SUCC … /* Fields of HNS_ROCE_OPC_CFG_BT_ATTR */ #define CFG_BT_ATTR_QPC_BA_PGSZ … #define CFG_BT_ATTR_QPC_BUF_PGSZ … #define CFG_BT_ATTR_QPC_HOPNUM … #define CFG_BT_ATTR_SRQC_BA_PGSZ … #define CFG_BT_ATTR_SRQC_BUF_PGSZ … #define CFG_BT_ATTR_SRQC_HOPNUM … #define CFG_BT_ATTR_CQC_BA_PGSZ … #define CFG_BT_ATTR_CQC_BUF_PGSZ … #define CFG_BT_ATTR_CQC_HOPNUM … #define CFG_BT_ATTR_MPT_BA_PGSZ … #define CFG_BT_ATTR_MPT_BUF_PGSZ … #define CFG_BT_ATTR_MPT_HOPNUM … #define CFG_BT_ATTR_SCCC_BA_PGSZ … #define CFG_BT_ATTR_SCCC_BUF_PGSZ … #define CFG_BT_ATTR_SCCC_HOPNUM … /* Fields of HNS_ROCE_OPC_CFG_ENTRY_SIZE */ #define CFG_HEM_ENTRY_SIZE_TYPE … enum { … }; #define CFG_HEM_ENTRY_SIZE_VALUE … /* Fields of HNS_ROCE_OPC_CFG_GMV_BT */ #define CFG_GMV_BT_BA_L … #define CFG_GMV_BT_BA_H … #define CFG_GMV_BT_IDX … /* Fields of HNS_ROCE_QUERY_RAM_ECC */ #define QUERY_RAM_ECC_1BIT_ERR … #define QUERY_RAM_ECC_RES_TYPE … #define QUERY_RAM_ECC_TAG … struct hns_roce_cfg_sgid_tb { … }; #define SGID_TB_FIELD_LOC(h, l) … #define CFG_SGID_TB_TABLE_IDX … #define CFG_SGID_TB_VF_SGID_TYPE … struct hns_roce_cfg_smac_tb { … }; #define SMAC_TB_FIELD_LOC(h, l) … #define CFG_SMAC_TB_IDX … #define CFG_SMAC_TB_VF_SMAC_H … struct hns_roce_cfg_gmv_tb_a { … }; #define GMV_TB_A_FIELD_LOC(h, l) … #define GMV_TB_A_VF_SGID_TYPE … #define GMV_TB_A_VF_VLAN_EN … #define GMV_TB_A_VF_VLAN_ID … struct hns_roce_cfg_gmv_tb_b { … }; #define GMV_TB_B_FIELD_LOC(h, l) … #define GMV_TB_B_SMAC_H … #define GMV_TB_B_SGID_IDX … #define HNS_ROCE_QUERY_PF_CAPS_CMD_NUM … struct hns_roce_query_pf_caps_a { … }; struct hns_roce_query_pf_caps_b { … }; struct hns_roce_query_pf_caps_c { … }; #define PF_CAPS_C_FIELD_LOC(h, l) … #define PF_CAPS_C_NUM_PDS … #define PF_CAPS_C_CAP_FLAGS … #define PF_CAPS_C_NUM_CQS … #define PF_CAPS_C_MAX_GID … #define PF_CAPS_C_CQ_DEPTH … #define PF_CAPS_C_NUM_XRCDS … #define PF_CAPS_C_NUM_MRWS … #define PF_CAPS_C_NUM_QPS … #define PF_CAPS_C_MAX_ORD … struct hns_roce_query_pf_caps_d { … }; #define PF_CAPS_D_FIELD_LOC(h, l) … #define PF_CAPS_D_NUM_SRQS … #define PF_CAPS_D_RQWQE_HOP_NUM … #define PF_CAPS_D_EX_SGE_HOP_NUM … #define PF_CAPS_D_SQWQE_HOP_NUM … #define PF_CAPS_D_CONG_CAP … #define PF_CAPS_D_CEQ_DEPTH … #define PF_CAPS_D_NUM_CEQS … #define PF_CAPS_D_AEQ_DEPTH … #define PF_CAPS_D_AEQ_ARM_ST … #define PF_CAPS_D_CEQ_ARM_ST … #define PF_CAPS_D_DEFAULT_ALG … #define PF_CAPS_D_RSV_PDS … #define PF_CAPS_D_NUM_UARS … #define PF_CAPS_D_RSV_QPS … #define PF_CAPS_D_RSV_UARS … #define HNS_ROCE_CAP_FLAGS_EX_SHIFT … struct hns_roce_congestion_algorithm { … }; struct hns_roce_query_pf_caps_e { … }; #define PF_CAPS_E_FIELD_LOC(h, l) … #define PF_CAPS_E_RSV_MRWS … #define PF_CAPS_E_CHUNK_SIZE_SHIFT … #define PF_CAPS_E_RSV_CQS … #define PF_CAPS_E_RSV_XRCDS … #define PF_CAPS_E_RSV_SRQS … #define PF_CAPS_E_RSV_LKEYS … struct hns_roce_cmq_req { … }; #define CMQ_REQ_FIELD_LOC(h, l) … struct hns_roce_cmq_desc { … }; struct hns_roce_v2_cmq_ring { … }; struct hns_roce_v2_cmq { … }; struct hns_roce_link_table { … }; #define HNS_ROCE_EXT_LLM_ENTRY(addr, id) … #define HNS_ROCE_EXT_LLM_MIN_PAGES(que_num) … struct hns_roce_v2_free_mr { … }; struct hns_roce_v2_priv { … }; struct hns_roce_dip { … }; struct fmea_ram_ecc { … }; /* only for RNR timeout issue of HIP08 */ #define HNS_ROCE_CLOCK_ADJUST … #define HNS_ROCE_MAX_CQ_PERIOD_HIP08 … #define HNS_ROCE_MAX_EQ_PERIOD … #define HNS_ROCE_RNR_TIMER_10NS … #define HNS_ROCE_1US_CFG … #define HNS_ROCE_1NS_CFG … #define HNS_ROCE_AEQ_DEFAULT_BURST_NUM … #define HNS_ROCE_AEQ_DEFAULT_INTERVAL … #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM … #define HNS_ROCE_CEQ_DEFAULT_INTERVAL … #define HNS_ROCE_V2_EQ_STATE_INVALID … #define HNS_ROCE_V2_EQ_STATE_VALID … #define HNS_ROCE_V2_EQ_STATE_OVERFLOW … #define HNS_ROCE_V2_EQ_STATE_FAILURE … #define HNS_ROCE_V2_EQ_OVER_IGNORE_0 … #define HNS_ROCE_V2_EQ_OVER_IGNORE_1 … #define HNS_ROCE_V2_EQ_COALESCE_0 … #define HNS_ROCE_V2_EQ_COALESCE_1 … #define HNS_ROCE_V2_EQ_FIRED … #define HNS_ROCE_V2_EQ_ARMED … #define HNS_ROCE_V2_EQ_ALWAYS_ARMED … #define HNS_ROCE_EQ_INIT_EQE_CNT … #define HNS_ROCE_EQ_INIT_PROD_IDX … #define HNS_ROCE_EQ_INIT_REPORT_TIMER … #define HNS_ROCE_EQ_INIT_MSI_IDX … #define HNS_ROCE_EQ_INIT_CONS_IDX … #define HNS_ROCE_EQ_INIT_NXT_EQE_BA … #define HNS_ROCE_V2_COMP_EQE_NUM … #define HNS_ROCE_V2_ASYNC_EQE_NUM … #define HNS_ROCE_V2_VF_INT_ST_AEQ_OVERFLOW_S … #define HNS_ROCE_EQ_DB_CMD_AEQ … #define HNS_ROCE_EQ_DB_CMD_AEQ_ARMED … #define HNS_ROCE_EQ_DB_CMD_CEQ … #define HNS_ROCE_EQ_DB_CMD_CEQ_ARMED … #define EQ_ENABLE … #define EQ_DISABLE … #define EQ_REG_OFFSET … #define HNS_ROCE_INT_NAME_LEN … #define HNS_ROCE_V2_EQN_M … #define HNS_ROCE_V2_VF_ABN_INT_EN_S … #define HNS_ROCE_V2_VF_ABN_INT_EN_M … #define HNS_ROCE_V2_VF_ABN_INT_ST_M … #define HNS_ROCE_V2_VF_ABN_INT_CFG_M … #define HNS_ROCE_V2_VF_EVENT_INT_EN_M … struct hns_roce_eq_context { … }; #define EQC_FIELD_LOC(h, l) … #define EQC_EQ_ST … #define EQC_EQE_HOP_NUM … #define EQC_OVER_IGNORE … #define EQC_COALESCE … #define EQC_ARM_ST … #define EQC_EQN … #define EQC_EQE_CNT … #define EQC_EQE_BA_PG_SZ … #define EQC_EQE_BUF_PG_SZ … #define EQC_EQ_PROD_INDX … #define EQC_EQ_MAX_CNT … #define EQC_EQ_PERIOD … #define EQC_EQE_REPORT_TIMER … #define EQC_EQE_BA_L … #define EQC_EQE_BA_H … #define EQC_SHIFT … #define EQC_MSI_INDX … #define EQC_CUR_EQE_BA_L … #define EQC_CUR_EQE_BA_M … #define EQC_CUR_EQE_BA_H … #define EQC_EQ_CONS_INDX … #define EQC_NEX_EQE_BA_L … #define EQC_NEX_EQE_BA_H … #define EQC_EQE_SIZE … #define MAX_SERVICE_LEVEL … struct hns_roce_wqe_atomic_seg { … }; struct hns_roce_sccc_clr { … }; struct hns_roce_sccc_clr_done { … }; int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata); static inline void hns_roce_write64(struct hns_roce_dev *hr_dev, __le32 val[2], void __iomem *dest) { … } #endif
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