/* * Broadcom NetXtreme-E RoCE driver. * * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term * Broadcom refers to Broadcom Limited and/or its subsidiaries. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * BSD license below: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Description: QPLib resource manager (header) */ #ifndef __BNXT_QPLIB_RES_H__ #define __BNXT_QPLIB_RES_H__ extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero; #define CHIP_NUM_57508 … #define CHIP_NUM_57504 … #define CHIP_NUM_57502 … #define CHIP_NUM_58818 … #define CHIP_NUM_57608 … #define BNXT_QPLIB_DBR_VALID … #define BNXT_QPLIB_DBR_EPOCH_SHIFT … #define BNXT_QPLIB_DBR_TOGGLE_SHIFT … struct bnxt_qplib_drv_modes { … }; enum bnxt_re_toggle_modes { … }; struct bnxt_qplib_chip_ctx { … }; struct bnxt_qplib_db_pacing_data { … }; #define BNXT_QPLIB_DBR_PF_DB_OFFSET … #define BNXT_QPLIB_DBR_VF_DB_OFFSET … #define PTR_CNT_PER_PG … #define PTR_MAX_IDX_PER_PG … #define PTR_PG(x) … #define PTR_IDX(x) … #define HWQ_CMP(idx, hwq) … #define HWQ_FREE_SLOTS(hwq) … enum bnxt_qplib_hwq_type { … }; #define MAX_PBL_LVL_0_PGS … #define MAX_PBL_LVL_1_PGS … #define MAX_PBL_LVL_1_PGS_SHIFT … #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 … #define MAX_PBL_LVL_2_PGS … #define MAX_PDL_LVL_SHIFT … enum bnxt_qplib_pbl_lvl { … }; #define ROCE_PG_SIZE_4K … #define ROCE_PG_SIZE_8K … #define ROCE_PG_SIZE_64K … #define ROCE_PG_SIZE_2M … #define ROCE_PG_SIZE_8M … #define ROCE_PG_SIZE_1G … enum bnxt_qplib_hwrm_pg_size { … }; struct bnxt_qplib_reg_desc { … }; struct bnxt_qplib_pbl { … }; struct bnxt_qplib_sg_info { … }; struct bnxt_qplib_hwq_attr { … }; struct bnxt_qplib_hwq { … }; struct bnxt_qplib_db_info { … }; enum bnxt_qplib_db_info_flags_mask { … }; enum bnxt_qplib_db_epoch_flag_shift { … }; /* Tables */ struct bnxt_qplib_pd_tbl { … }; struct bnxt_qplib_sgid_tbl { … }; enum { … }; struct bnxt_qplib_dpi { … }; struct bnxt_qplib_dpi_tbl { … }; struct bnxt_qplib_stats { … }; struct bnxt_qplib_vf_res { … }; #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE … #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE … #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE … #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE … #define MAX_TQM_ALLOC_REQ … #define MAX_TQM_ALLOC_BLK_SIZE … struct bnxt_qplib_tqm_ctx { … }; struct bnxt_qplib_ctx { … }; struct bnxt_qplib_res { … }; static inline bool bnxt_qplib_is_chip_gen_p7(struct bnxt_qplib_chip_ctx *cctx) { … } static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx) { … } static inline bool bnxt_qplib_is_chip_gen_p5_p7(struct bnxt_qplib_chip_ctx *cctx) { … } static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res) { … } static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx) { … } static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq) { … } static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq, u32 indx, u64 *pg) { … } static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx) { … } #define to_bnxt_qplib(ptr, type, member) … struct bnxt_qplib_pd; struct bnxt_qplib_dev_attr; void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, struct bnxt_qplib_hwq *hwq); int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, struct bnxt_qplib_hwq_attr *hwq_attr); int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res, struct bnxt_qplib_pd *pd); int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, struct bnxt_qplib_pd_tbl *pd_tbl, struct bnxt_qplib_pd *pd); int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res, struct bnxt_qplib_dpi *dpi, void *app, u8 type); int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, struct bnxt_qplib_dpi *dpi); void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res); int bnxt_qplib_init_res(struct bnxt_qplib_res *res); void bnxt_qplib_free_res(struct bnxt_qplib_res *res); int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, struct net_device *netdev, struct bnxt_qplib_dev_attr *dev_attr); void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx); int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx, bool virt_fn, bool is_p5); int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res); void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res); int bnxt_qplib_determine_atomics(struct pci_dev *dev); static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_db_info *dbinfo, struct bnxt_qplib_hwq *hwq, u32 cnt) { … } static inline void bnxt_qplib_hwq_incr_cons(u32 max_elements, u32 *cons, u32 cnt, u32 *dbinfo_flags) { … } static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info, bool arm) { … } #define BNXT_QPLIB_INIT_DBHDR(xid, type, indx, toggle) … static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info, u32 type) { … } static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info, u32 type) { … } static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info, u32 type) { … } static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info, u32 th) { … } static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info, struct bnxt_qplib_chip_ctx *cctx, bool arm) { … } static inline bool _is_ext_stats_supported(u16 dev_cap_flags) { … } static inline bool _is_hw_retx_supported(u16 dev_cap_flags) { … } #define BNXT_RE_HW_RETX(a) … static inline bool _is_host_msn_table(u16 dev_cap_ext_flags2) { … } static inline u8 bnxt_qplib_dbr_pacing_en(struct bnxt_qplib_chip_ctx *cctx) { … } #endif /* __BNXT_QPLIB_RES_H__ */
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