/* SPDX-License-Identifier: GPL-2.0 */ /* * This header provides clock numbers for the ingenic,x1830-cgu DT binding. * * They are roughly ordered as: * - external clocks * - PLLs * - muxes/dividers in the order they appear in the x1830 programmers manual * - gates in order of their bit in the CLKGR* registers */ #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ #define __DT_BINDINGS_CLOCK_X1830_CGU_H__ #define X1830_CLK_EXCLK … #define X1830_CLK_RTCLK … #define X1830_CLK_APLL … #define X1830_CLK_MPLL … #define X1830_CLK_EPLL … #define X1830_CLK_VPLL … #define X1830_CLK_OTGPHY … #define X1830_CLK_SCLKA … #define X1830_CLK_CPUMUX … #define X1830_CLK_CPU … #define X1830_CLK_L2CACHE … #define X1830_CLK_AHB0 … #define X1830_CLK_AHB2PMUX … #define X1830_CLK_AHB2 … #define X1830_CLK_PCLK … #define X1830_CLK_DDR … #define X1830_CLK_MAC … #define X1830_CLK_LCD … #define X1830_CLK_MSCMUX … #define X1830_CLK_MSC0 … #define X1830_CLK_MSC1 … #define X1830_CLK_SSIPLL … #define X1830_CLK_SSIPLL_DIV2 … #define X1830_CLK_SSIMUX … #define X1830_CLK_EMC … #define X1830_CLK_EFUSE … #define X1830_CLK_OTG … #define X1830_CLK_SSI0 … #define X1830_CLK_SMB0 … #define X1830_CLK_SMB1 … #define X1830_CLK_SMB2 … #define X1830_CLK_UART0 … #define X1830_CLK_UART1 … #define X1830_CLK_SSI1 … #define X1830_CLK_SFC … #define X1830_CLK_PDMA … #define X1830_CLK_TCU … #define X1830_CLK_DTRNG … #define X1830_CLK_OST … #define X1830_CLK_EXCLK_DIV512 … #define X1830_CLK_RTC … #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
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