linux/drivers/clk/ingenic/x1830-cgu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * X1830 SoC CGU driver
 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>

#include <dt-bindings/clock/ingenic,x1830-cgu.h>

#include "cgu.h"
#include "pm.h"

/* CGU register offsets */
#define CGU_REG_CPCCR …
#define CGU_REG_CPPCR …
#define CGU_REG_APLL …
#define CGU_REG_MPLL …
#define CGU_REG_CLKGR0 …
#define CGU_REG_OPCR …
#define CGU_REG_CLKGR1 …
#define CGU_REG_DDRCDR …
#define CGU_REG_USBPCR …
#define CGU_REG_USBRDT …
#define CGU_REG_USBVBFIL …
#define CGU_REG_USBPCR1 …
#define CGU_REG_MACCDR …
#define CGU_REG_EPLL …
#define CGU_REG_I2SCDR …
#define CGU_REG_LPCDR …
#define CGU_REG_MSC0CDR …
#define CGU_REG_I2SCDR1 …
#define CGU_REG_SSICDR …
#define CGU_REG_CIMCDR …
#define CGU_REG_MSC1CDR …
#define CGU_REG_CMP_INTR …
#define CGU_REG_CMP_INTRE …
#define CGU_REG_DRCG …
#define CGU_REG_CPCSR …
#define CGU_REG_VPLL …
#define CGU_REG_MACPHYC …

/* bits within the OPCR register */
#define OPCR_GATE_USBPHYCLK …
#define OPCR_SPENDN0 …
#define OPCR_SPENDN1 …

/* bits within the USBPCR register */
#define USBPCR_SIDDQ …
#define USBPCR_OTG_DISABLE …

static struct ingenic_cgu *cgu;

static int x1830_usb_phy_enable(struct clk_hw *hw)
{ … }

static void x1830_usb_phy_disable(struct clk_hw *hw)
{ … }

static int x1830_usb_phy_is_enabled(struct clk_hw *hw)
{ … }

static const struct clk_ops x1830_otg_phy_ops = …;

static const s8 pll_od_encoding[64] = …;

static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = …;

static void __init x1830_cgu_init(struct device_node *np)
{ … }
/*
 * CGU has some children devices, this is useful for probing children devices
 * in the case where the device node is compatible with "simple-mfd".
 */
CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);