// SPDX-License-Identifier: GPL-2.0 /* * X1000 SoC CGU driver * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <[email protected]> */ #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/io.h> #include <linux/of.h> #include <linux/rational.h> #include <dt-bindings/clock/ingenic,x1000-cgu.h> #include "cgu.h" #include "pm.h" /* CGU register offsets */ #define CGU_REG_CPCCR … #define CGU_REG_APLL … #define CGU_REG_MPLL … #define CGU_REG_CLKGR … #define CGU_REG_OPCR … #define CGU_REG_DDRCDR … #define CGU_REG_USBPCR … #define CGU_REG_USBPCR1 … #define CGU_REG_USBCDR … #define CGU_REG_MACCDR … #define CGU_REG_I2SCDR … #define CGU_REG_LPCDR … #define CGU_REG_MSC0CDR … #define CGU_REG_I2SCDR1 … #define CGU_REG_SSICDR … #define CGU_REG_CIMCDR … #define CGU_REG_PCMCDR … #define CGU_REG_MSC1CDR … #define CGU_REG_CMP_INTR … #define CGU_REG_CMP_INTRE … #define CGU_REG_DRCG … #define CGU_REG_CPCSR … #define CGU_REG_PCMCDR1 … #define CGU_REG_MACPHYC … /* bits within the OPCR register */ #define OPCR_SPENDN0 … #define OPCR_SPENDN1 … /* bits within the USBPCR register */ #define USBPCR_SIDDQ … #define USBPCR_OTG_DISABLE … /* bits within the USBPCR1 register */ #define USBPCR1_REFCLKSEL_SHIFT … #define USBPCR1_REFCLKSEL_MASK … #define USBPCR1_REFCLKSEL_CORE … #define USBPCR1_REFCLKDIV_SHIFT … #define USBPCR1_REFCLKDIV_MASK … #define USBPCR1_REFCLKDIV_48 … #define USBPCR1_REFCLKDIV_24 … #define USBPCR1_REFCLKDIV_12 … static struct ingenic_cgu *cgu; static unsigned long x1000_otg_phy_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long x1000_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long *parent_rate) { … } static int x1000_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, unsigned long parent_rate) { … } static int x1000_usb_phy_enable(struct clk_hw *hw) { … } static void x1000_usb_phy_disable(struct clk_hw *hw) { … } static int x1000_usb_phy_is_enabled(struct clk_hw *hw) { … } static const struct clk_ops x1000_otg_phy_ops = …; static void x1000_i2spll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate, unsigned int *pm, unsigned int *pn, unsigned int *pod) { … } static void x1000_i2spll_set_rate_hook(const struct ingenic_cgu_pll_info *pll_info, unsigned long rate, unsigned long parent_rate) { … } static const s8 pll_od_encoding[8] = …; static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = …; static void __init x1000_cgu_init(struct device_node *np) { … } /* * CGU has some children devices, this is useful for probing children devices * in the case where the device node is compatible with "simple-mfd". */ CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
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