/* * Copyright (c) 2016-2017 Hisilicon Limited. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include <linux/acpi.h> #include <linux/etherdevice.h> #include <linux/interrupt.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/workqueue.h> #include <net/addrconf.h> #include <rdma/ib_addr.h> #include <rdma/ib_cache.h> #include <rdma/ib_umem.h> #include <rdma/uverbs_ioctl.h> #include "hnae3.h" #include "hns_roce_common.h" #include "hns_roce_device.h" #include "hns_roce_cmd.h" #include "hns_roce_hem.h" #include "hns_roce_hw_v2.h" enum { … }; enum ecc_resource_type { … }; static const struct { … } fmea_ram_res[] = …; static inline void set_data_seg_v2(struct hns_roce_v2_wqe_data_seg *dseg, struct ib_sge *sg) { … } /* * mapped-value = 1 + real-value * The hns wr opcode real value is start from 0, In order to distinguish between * initialized and uninitialized map values, we plus 1 to the actual value when * defining the mapping, so that the validity can be identified by checking the * mapped value is greater than 0. */ #define HR_OPC_MAP(ib_key, hr_key) … static const u32 hns_roce_op_code[] = …; static u32 to_hr_opcode(u32 ib_opcode) { … } static void set_frmr_seg(struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, const struct ib_reg_wr *wr) { … } static void set_atomic_seg(const struct ib_send_wr *wr, struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, unsigned int valid_num_sge) { … } static int fill_ext_sge_inl_data(struct hns_roce_qp *qp, const struct ib_send_wr *wr, unsigned int *sge_idx, u32 msg_len) { … } static void set_extend_sge(struct hns_roce_qp *qp, struct ib_sge *sge, unsigned int *sge_ind, unsigned int cnt) { … } static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len) { … } static int set_rc_inl(struct hns_roce_qp *qp, const struct ib_send_wr *wr, struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, unsigned int *sge_idx) { … } static int set_rwqe_data_seg(struct ib_qp *ibqp, const struct ib_send_wr *wr, struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, unsigned int *sge_ind, unsigned int valid_num_sge) { … } static int check_send_valid(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) { … } static unsigned int calc_wr_sge_num(const struct ib_send_wr *wr, unsigned int *sge_len) { … } static __le32 get_immtdata(const struct ib_send_wr *wr) { … } static int set_ud_opcode(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, const struct ib_send_wr *wr) { … } static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe, struct hns_roce_ah *ah) { … } static inline int set_ud_wqe(struct hns_roce_qp *qp, const struct ib_send_wr *wr, void *wqe, unsigned int *sge_idx, unsigned int owner_bit) { … } static int set_rc_opcode(struct hns_roce_dev *hr_dev, struct hns_roce_v2_rc_send_wqe *rc_sq_wqe, const struct ib_send_wr *wr) { … } static inline int set_rc_wqe(struct hns_roce_qp *qp, const struct ib_send_wr *wr, void *wqe, unsigned int *sge_idx, unsigned int owner_bit) { … } static inline void update_sq_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp) { … } static inline void update_rq_db(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp) { … } static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, u64 __iomem *dest) { … } static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, void *wqe) { … } static int hns_roce_v2_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) { … } static int check_recv_valid(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) { … } static void fill_recv_sge_to_wqe(const struct ib_recv_wr *wr, void *wqe, u32 max_sge, bool rsv) { … } static void fill_rq_wqe(struct hns_roce_qp *hr_qp, const struct ib_recv_wr *wr, u32 wqe_idx, u32 max_sge) { … } static int hns_roce_v2_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr) { … } static void *get_srq_wqe_buf(struct hns_roce_srq *srq, u32 n) { … } static void *get_idx_buf(struct hns_roce_idx_que *idx_que, u32 n) { … } static void hns_roce_free_srq_wqe(struct hns_roce_srq *srq, u32 wqe_index) { … } static int hns_roce_srqwq_overflow(struct hns_roce_srq *srq) { … } static int check_post_srq_valid(struct hns_roce_srq *srq, u32 max_sge, const struct ib_recv_wr *wr) { … } static int get_srq_wqe_idx(struct hns_roce_srq *srq, u32 *wqe_idx) { … } static void fill_wqe_idx(struct hns_roce_srq *srq, unsigned int wqe_idx) { … } static void update_srq_db(struct hns_roce_srq *srq) { … } static int hns_roce_v2_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, const struct ib_recv_wr **bad_wr) { … } static u32 hns_roce_v2_cmd_hw_reseted(struct hns_roce_dev *hr_dev, unsigned long instance_stage, unsigned long reset_stage) { … } static u32 hns_roce_v2_cmd_hw_resetting(struct hns_roce_dev *hr_dev, unsigned long instance_stage, unsigned long reset_stage) { … } static u32 hns_roce_v2_cmd_sw_resetting(struct hns_roce_dev *hr_dev) { … } static u32 check_aedev_reset_status(struct hns_roce_dev *hr_dev, struct hnae3_handle *handle) { … } static bool check_device_is_in_reset(struct hns_roce_dev *hr_dev) { … } static bool v2_chk_mbox_is_avail(struct hns_roce_dev *hr_dev, bool *busy) { … } static int hns_roce_alloc_cmq_desc(struct hns_roce_dev *hr_dev, struct hns_roce_v2_cmq_ring *ring) { … } static void hns_roce_free_cmq_desc(struct hns_roce_dev *hr_dev, struct hns_roce_v2_cmq_ring *ring) { … } static int init_csq(struct hns_roce_dev *hr_dev, struct hns_roce_v2_cmq_ring *csq) { … } static int hns_roce_v2_cmq_init(struct hns_roce_dev *hr_dev) { … } static void hns_roce_v2_cmq_exit(struct hns_roce_dev *hr_dev) { … } static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, enum hns_roce_opcode_type opcode, bool is_read) { … } static int hns_roce_cmq_csq_done(struct hns_roce_dev *hr_dev) { … } static void update_cmdq_status(struct hns_roce_dev *hr_dev) { … } static int hns_roce_cmd_err_convert_errno(u16 desc_ret) { … } static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout) { … } static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode) { … } static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, struct hns_roce_cmq_desc *desc, int num) { … } static int hns_roce_cmq_send(struct hns_roce_dev *hr_dev, struct hns_roce_cmq_desc *desc, int num) { … } static int config_hem_ba_to_hw(struct hns_roce_dev *hr_dev, dma_addr_t base_addr, u8 cmd, unsigned long tag) { … } static int hns_roce_cmq_query_hw_info(struct hns_roce_dev *hr_dev) { … } static void func_clr_hw_resetting_state(struct hns_roce_dev *hr_dev, struct hnae3_handle *handle) { … } static void func_clr_sw_resetting_state(struct hns_roce_dev *hr_dev, struct hnae3_handle *handle) { … } static void hns_roce_func_clr_rst_proc(struct hns_roce_dev *hr_dev, int retval, int flag) { … } static void __hns_roce_function_clear(struct hns_roce_dev *hr_dev, int vf_id) { … } static int hns_roce_free_vf_resource(struct hns_roce_dev *hr_dev, int vf_id) { … } static void hns_roce_function_clear(struct hns_roce_dev *hr_dev) { … } static int hns_roce_clear_extdb_list_info(struct hns_roce_dev *hr_dev) { … } static int hns_roce_query_fw_ver(struct hns_roce_dev *hr_dev) { … } static int hns_roce_query_func_info(struct hns_roce_dev *hr_dev) { … } static int hns_roce_hw_v2_query_counter(struct hns_roce_dev *hr_dev, u64 *stats, u32 port, int *num_counters) { … } static int hns_roce_config_global_param(struct hns_roce_dev *hr_dev) { … } static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) { … } static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) { … } static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev) { … } static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev) { … } static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, u32 vf_id) { … } static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev) { … } static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) { … } static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) { … } static int hns_roce_v2_set_bt(struct hns_roce_dev *hr_dev) { … } static void calc_pg_sz(u32 obj_num, u32 obj_size, u32 hop_num, u32 ctx_bt_num, u32 *buf_page_size, u32 *bt_page_size, u32 hem_type) { … } static void set_hem_page_size(struct hns_roce_dev *hr_dev) { … } /* Apply all loaded caps before setting to hardware */ static void apply_func_caps(struct hns_roce_dev *hr_dev) { … } static int hns_roce_query_caps(struct hns_roce_dev *hr_dev) { … } static int config_hem_entry_size(struct hns_roce_dev *hr_dev, u32 type, u32 val) { … } static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) { … } static int hns_roce_v2_vf_profile(struct hns_roce_dev *hr_dev) { … } static int hns_roce_v2_pf_profile(struct hns_roce_dev *hr_dev) { … } static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev) { … } static void config_llm_table(struct hns_roce_buf *data_buf, void *cfg_buf) { … } static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, struct hns_roce_link_table *table) { … } static struct hns_roce_link_table * alloc_link_table_buf(struct hns_roce_dev *hr_dev) { … } static void free_link_table_buf(struct hns_roce_dev *hr_dev, struct hns_roce_link_table *tbl) { … } static int hns_roce_init_link_table(struct hns_roce_dev *hr_dev) { … } static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev) { … } static void free_dip_list(struct hns_roce_dev *hr_dev) { … } static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev) { … } static struct ib_cq *free_mr_init_cq(struct hns_roce_dev *hr_dev) { … } static int free_mr_init_qp(struct hns_roce_dev *hr_dev, struct ib_cq *cq, struct ib_qp_init_attr *init_attr, int i) { … } static void free_mr_exit(struct hns_roce_dev *hr_dev) { … } static int free_mr_alloc_res(struct hns_roce_dev *hr_dev) { … } static int free_mr_modify_rsv_qp(struct hns_roce_dev *hr_dev, struct ib_qp_attr *attr, int sl_num) { … } static int free_mr_modify_qp(struct hns_roce_dev *hr_dev) { … } static int free_mr_init(struct hns_roce_dev *hr_dev) { … } static int get_hem_table(struct hns_roce_dev *hr_dev) { … } static void put_hem_table(struct hns_roce_dev *hr_dev) { … } static int hns_roce_v2_init(struct hns_roce_dev *hr_dev) { … } static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev) { … } static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev, struct hns_roce_mbox_msg *mbox_msg) { … } static int v2_wait_mbox_complete(struct hns_roce_dev *hr_dev, u32 timeout, u8 *complete_status) { … } static int v2_post_mbox(struct hns_roce_dev *hr_dev, struct hns_roce_mbox_msg *mbox_msg) { … } static int v2_poll_mbox_done(struct hns_roce_dev *hr_dev) { … } static void copy_gid(void *dest, const union ib_gid *gid) { … } static int config_sgid_table(struct hns_roce_dev *hr_dev, int gid_index, const union ib_gid *gid, enum hns_roce_sgid_type sgid_type) { … } static int config_gmv_table(struct hns_roce_dev *hr_dev, int gid_index, const union ib_gid *gid, enum hns_roce_sgid_type sgid_type, const struct ib_gid_attr *attr) { … } static int hns_roce_v2_set_gid(struct hns_roce_dev *hr_dev, int gid_index, const union ib_gid *gid, const struct ib_gid_attr *attr) { … } static int hns_roce_v2_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, const u8 *addr) { … } static int set_mtpt_pbl(struct hns_roce_dev *hr_dev, struct hns_roce_v2_mpt_entry *mpt_entry, struct hns_roce_mr *mr) { … } static int hns_roce_v2_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf, struct hns_roce_mr *mr) { … } static int hns_roce_v2_rereg_write_mtpt(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr, int flags, void *mb_buf) { … } static int hns_roce_v2_frmr_write_mtpt(void *mb_buf, struct hns_roce_mr *mr) { … } static int hns_roce_v2_mw_write_mtpt(void *mb_buf, struct hns_roce_mw *mw) { … } static int free_mr_post_send_lp_wqe(struct hns_roce_qp *hr_qp) { … } static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); static void free_mr_send_cmd_to_hw(struct hns_roce_dev *hr_dev) { … } static void hns_roce_v2_dereg_mr(struct hns_roce_dev *hr_dev) { … } static void *get_cqe_v2(struct hns_roce_cq *hr_cq, int n) { … } static void *get_sw_cqe_v2(struct hns_roce_cq *hr_cq, unsigned int n) { … } static inline void update_cq_db(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq) { … } static void __hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, struct hns_roce_srq *srq) { … } static void hns_roce_v2_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn, struct hns_roce_srq *srq) { … } static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, dma_addr_t dma_handle) { … } static int hns_roce_v2_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) { … } static int sw_comp(struct hns_roce_qp *hr_qp, struct hns_roce_wq *wq, int num_entries, struct ib_wc *wc) { … } static int hns_roce_v2_sw_poll_cq(struct hns_roce_cq *hr_cq, int num_entries, struct ib_wc *wc) { … } static void get_cqe_status(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, struct hns_roce_cq *cq, struct hns_roce_v2_cqe *cqe, struct ib_wc *wc) { … } static int get_cur_qp(struct hns_roce_cq *hr_cq, struct hns_roce_v2_cqe *cqe, struct hns_roce_qp **cur_qp) { … } /* * mapped-value = 1 + real-value * The ib wc opcode's real value is start from 0, In order to distinguish * between initialized and uninitialized map values, we plus 1 to the actual * value when defining the mapping, so that the validity can be identified by * checking whether the mapped value is greater than 0. */ #define HR_WC_OP_MAP(hr_key, ib_key) … static const u32 wc_send_op_map[] = …; static int to_ib_wc_send_op(u32 hr_opcode) { … } static const u32 wc_recv_op_map[] = …; static int to_ib_wc_recv_op(u32 hr_opcode) { … } static void fill_send_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) { … } static int fill_recv_wc(struct ib_wc *wc, struct hns_roce_v2_cqe *cqe) { … } static int hns_roce_v2_poll_one(struct hns_roce_cq *hr_cq, struct hns_roce_qp **cur_qp, struct ib_wc *wc) { … } static int hns_roce_v2_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) { … } static int get_op_for_set_hem(struct hns_roce_dev *hr_dev, u32 type, u32 step_idx, u8 *mbox_cmd) { … } static int config_gmv_ba_to_hw(struct hns_roce_dev *hr_dev, unsigned long obj, dma_addr_t base_addr) { … } static int set_hem_to_hw(struct hns_roce_dev *hr_dev, int obj, dma_addr_t base_addr, u32 hem_type, u32 step_idx) { … } static int hns_roce_v2_set_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem_table *table, int obj, u32 step_idx) { … } static int hns_roce_v2_clear_hem(struct hns_roce_dev *hr_dev, struct hns_roce_hem_table *table, int tag, u32 step_idx) { … } static int hns_roce_v2_qp_modify(struct hns_roce_dev *hr_dev, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask, struct hns_roce_qp *hr_qp) { … } static void set_access_flags(struct hns_roce_qp *hr_qp, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask, const struct ib_qp_attr *attr, int attr_mask) { … } static void set_qpc_wqe_cnt(struct hns_roce_qp *hr_qp, struct hns_roce_v2_qp_context *context) { … } static inline int get_cqn(struct ib_cq *ib_cq) { … } static inline int get_pdn(struct ib_pd *ib_pd) { … } static void modify_qp_reset_to_init(struct ib_qp *ibqp, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static void modify_qp_init_to_init(struct ib_qp *ibqp, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static int config_qp_rq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static int config_qp_sq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static inline enum ib_mtu get_mtu(struct ib_qp *ibqp, const struct ib_qp_attr *attr) { … } static int modify_qp_init_to_rtr(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask, struct ib_udata *udata) { … } static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr, u32 *dip_idx) { … } enum { … }; enum { … }; enum { … }; enum { … }; enum { … }; static int check_cong_type(struct ib_qp *ibqp, struct hns_roce_congestion_algorithm *cong_alg) { … } static int fill_cong_field(struct ib_qp *ibqp, const struct ib_qp_attr *attr, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static int hns_roce_hw_v2_get_dscp(struct hns_roce_dev *hr_dev, u8 dscp, u8 *tc_mode, u8 *priority) { … } bool check_sl_valid(struct hns_roce_dev *hr_dev, u8 sl) { … } static int hns_roce_set_sl(struct ib_qp *ibqp, const struct ib_qp_attr *attr, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static int hns_roce_v2_set_path(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static bool check_qp_state(enum ib_qp_state cur_state, enum ib_qp_state new_state) { … } static int hns_roce_v2_set_abs_fields(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, enum ib_qp_state new_state, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask, struct ib_udata *udata) { … } static bool check_qp_timeout_cfg_range(struct hns_roce_dev *hr_dev, u8 *timeout) { … } static int hns_roce_v2_set_opt_fields(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static void hns_roce_v2_record_opt_fields(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask) { … } static void clear_qp(struct hns_roce_qp *hr_qp) { … } static void v2_set_flushed_fields(struct ib_qp *ibqp, struct hns_roce_v2_qp_context *context, struct hns_roce_v2_qp_context *qpc_mask) { … } static int hns_roce_v2_modify_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, int attr_mask, enum ib_qp_state cur_state, enum ib_qp_state new_state, struct ib_udata *udata) { … } static int to_ib_qp_st(enum hns_roce_v2_qp_state state) { … } static int hns_roce_v2_query_qpc(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer) { … } static int hns_roce_v2_query_srqc(struct hns_roce_dev *hr_dev, u32 srqn, void *buffer) { … } static int hns_roce_v2_query_sccc(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer) { … } static u8 get_qp_timeout_attr(struct hns_roce_dev *hr_dev, struct hns_roce_v2_qp_context *context) { … } static int hns_roce_v2_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) { … } static inline int modify_qp_is_ok(struct hns_roce_qp *hr_qp) { … } static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, struct ib_udata *udata) { … } int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) { … } static int hns_roce_v2_qp_flow_control_init(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp) { … } #define DMA_IDX_SHIFT … #define DMA_WQE_SHIFT … static int hns_roce_v2_write_srqc_index_queue(struct hns_roce_srq *srq, struct hns_roce_srq_context *ctx) { … } static int hns_roce_v2_write_srqc(struct hns_roce_srq *srq, void *mb_buf) { … } static int hns_roce_v2_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr, enum ib_srq_attr_mask srq_attr_mask, struct ib_udata *udata) { … } static int hns_roce_v2_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) { … } static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) { … } static int hns_roce_v2_query_cqc(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer) { … } static int hns_roce_v2_query_mpt(struct hns_roce_dev *hr_dev, u32 key, void *buffer) { … } static void hns_roce_irq_work_handle(struct work_struct *work) { … } static void hns_roce_v2_init_irq_work(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, u32 queue_num) { … } static void update_eq_db(struct hns_roce_eq *eq) { … } static struct hns_roce_aeqe *next_aeqe_sw_v2(struct hns_roce_eq *eq) { … } static irqreturn_t hns_roce_v2_aeq_int(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) { … } static struct hns_roce_ceqe *next_ceqe_sw_v2(struct hns_roce_eq *eq) { … } static irqreturn_t hns_roce_v2_ceq_int(struct hns_roce_eq *eq) { … } static irqreturn_t hns_roce_v2_msix_interrupt_eq(int irq, void *eq_ptr) { … } static irqreturn_t abnormal_interrupt_basic(struct hns_roce_dev *hr_dev, u32 int_st) { … } static int fmea_ram_ecc_query(struct hns_roce_dev *hr_dev, struct fmea_ram_ecc *ecc_info) { … } static int fmea_recover_gmv(struct hns_roce_dev *hr_dev, u32 idx) { … } static u64 fmea_get_ram_res_addr(u32 res_type, __le64 *data) { … } static int fmea_recover_others(struct hns_roce_dev *hr_dev, u32 res_type, u32 index) { … } static void fmea_ram_ecc_recover(struct hns_roce_dev *hr_dev, struct fmea_ram_ecc *ecc_info) { … } static void fmea_ram_ecc_work(struct work_struct *ecc_work) { … } static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id) { … } static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, int eq_num, u32 enable_flag) { … } static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) { … } static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) { … } static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) { … } static int config_eqc(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, void *mb_buf) { … } static int alloc_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq) { … } static int hns_roce_v2_create_eq(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq, u8 eq_cmd) { … } static void hns_roce_ceq_work(struct work_struct *work) { … } static int __hns_roce_request_irq(struct hns_roce_dev *hr_dev, int irq_num, int comp_num, int aeq_num, int other_num) { … } static void __hns_roce_free_irq(struct hns_roce_dev *hr_dev) { … } static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) { … } static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) { … } static const struct ib_device_ops hns_roce_v2_dev_ops = …; static const struct ib_device_ops hns_roce_v2_dev_srq_ops = …; static const struct hns_roce_hw hns_roce_hw_v2 = …; static const struct pci_device_id hns_roce_hw_v2_pci_tbl[] = …; MODULE_DEVICE_TABLE(pci, hns_roce_hw_v2_pci_tbl); static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, struct hnae3_handle *handle) { … } static int __hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) { … } static void __hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, bool reset) { … } static int hns_roce_hw_v2_init_instance(struct hnae3_handle *handle) { … } static void hns_roce_hw_v2_uninit_instance(struct hnae3_handle *handle, bool reset) { … } static int hns_roce_hw_v2_reset_notify_down(struct hnae3_handle *handle) { … } static int hns_roce_hw_v2_reset_notify_init(struct hnae3_handle *handle) { … } static int hns_roce_hw_v2_reset_notify_uninit(struct hnae3_handle *handle) { … } static int hns_roce_hw_v2_reset_notify(struct hnae3_handle *handle, enum hnae3_reset_notify_type type) { … } static const struct hnae3_client_ops hns_roce_hw_v2_ops = …; static struct hnae3_client hns_roce_hw_v2_client = …; static int __init hns_roce_hw_v2_init(void) { … } static void __exit hns_roce_hw_v2_exit(void) { … } module_init(…) …; module_exit(hns_roce_hw_v2_exit); MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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