/* * Broadcom NetXtreme-E RoCE driver. * * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term * Broadcom refers to Broadcom Limited and/or its subsidiaries. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * BSD license below: * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Description: QPLib resource manager */ #define dev_fmt(fmt) … #include <linux/spinlock.h> #include <linux/pci.h> #include <linux/interrupt.h> #include <linux/inetdevice.h> #include <linux/dma-mapping.h> #include <linux/if_vlan.h> #include <linux/vmalloc.h> #include <rdma/ib_verbs.h> #include <rdma/ib_umem.h> #include "roce_hsi.h" #include "qplib_res.h" #include "qplib_sp.h" #include "qplib_rcfw.h" static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev, struct bnxt_qplib_stats *stats); static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev, struct bnxt_qplib_chip_ctx *cctx, struct bnxt_qplib_stats *stats); /* PBL */ static void __free_pbl(struct bnxt_qplib_res *res, struct bnxt_qplib_pbl *pbl, bool is_umem) { … } static void bnxt_qplib_fill_user_dma_pages(struct bnxt_qplib_pbl *pbl, struct bnxt_qplib_sg_info *sginfo) { … } static int __alloc_pbl(struct bnxt_qplib_res *res, struct bnxt_qplib_pbl *pbl, struct bnxt_qplib_sg_info *sginfo) { … } /* HWQ */ void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res, struct bnxt_qplib_hwq *hwq) { … } /* All HWQs are power of 2 in size */ int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq, struct bnxt_qplib_hwq_attr *hwq_attr) { … } /* Context Tables */ void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx) { … } static int bnxt_qplib_alloc_tqm_rings(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx) { … } static void bnxt_qplib_map_tqm_pgtbl(struct bnxt_qplib_tqm_ctx *ctx) { … } static int bnxt_qplib_setup_tqm_rings(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx) { … } /* * Routine: bnxt_qplib_alloc_ctx * Description: * Context tables are memories which are used by the chip fw. * The 6 tables defined are: * QPC ctx - holds QP states * MRW ctx - holds memory region and window * SRQ ctx - holds shared RQ states * CQ ctx - holds completion queue states * TQM ctx - holds Tx Queue Manager context * TIM ctx - holds timer context * Depending on the size of the tbl requested, either a 1 Page Buffer List * or a 1-to-2-stage indirection Page Directory List + 1 PBL is used * instead. * Table might be employed as follows: * For 0 < ctx size <= 1 PAGE, 0 level of ind is used * For 1 PAGE < ctx size <= 512 entries size, 1 level of ind is used * For 512 < ctx size <= MAX, 2 levels of ind is used * Returns: * 0 if success, else -ERRORS */ int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res, struct bnxt_qplib_ctx *ctx, bool virt_fn, bool is_p5) { … } static void bnxt_qplib_free_sgid_tbl(struct bnxt_qplib_res *res, struct bnxt_qplib_sgid_tbl *sgid_tbl) { … } static int bnxt_qplib_alloc_sgid_tbl(struct bnxt_qplib_res *res, struct bnxt_qplib_sgid_tbl *sgid_tbl, u16 max) { sgid_tbl->tbl = kcalloc(max, sizeof(*sgid_tbl->tbl), GFP_KERNEL); if (!sgid_tbl->tbl) return -ENOMEM; sgid_tbl->hw_id = kcalloc(max, sizeof(u16), GFP_KERNEL); if (!sgid_tbl->hw_id) goto out_free1; sgid_tbl->ctx = kcalloc(max, sizeof(void *), GFP_KERNEL); if (!sgid_tbl->ctx) goto out_free2; sgid_tbl->vlan = kcalloc(max, sizeof(u8), GFP_KERNEL); if (!sgid_tbl->vlan) goto out_free3; sgid_tbl->max = max; return 0; out_free3: kfree(sgid_tbl->ctx); sgid_tbl->ctx = NULL; out_free2: kfree(sgid_tbl->hw_id); sgid_tbl->hw_id = NULL; out_free1: kfree(sgid_tbl->tbl); sgid_tbl->tbl = NULL; return -ENOMEM; }; static void bnxt_qplib_cleanup_sgid_tbl(struct bnxt_qplib_res *res, struct bnxt_qplib_sgid_tbl *sgid_tbl) { … } static void bnxt_qplib_init_sgid_tbl(struct bnxt_qplib_sgid_tbl *sgid_tbl, struct net_device *netdev) { … } /* PDs */ int bnxt_qplib_alloc_pd(struct bnxt_qplib_res *res, struct bnxt_qplib_pd *pd) { … } int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res, struct bnxt_qplib_pd_tbl *pdt, struct bnxt_qplib_pd *pd) { … } static void bnxt_qplib_free_pd_tbl(struct bnxt_qplib_pd_tbl *pdt) { … } static int bnxt_qplib_alloc_pd_tbl(struct bnxt_qplib_res *res, struct bnxt_qplib_pd_tbl *pdt, u32 max) { … } /* DPIs */ int bnxt_qplib_alloc_dpi(struct bnxt_qplib_res *res, struct bnxt_qplib_dpi *dpi, void *app, u8 type) { … } int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res, struct bnxt_qplib_dpi *dpi) { … } static void bnxt_qplib_free_dpi_tbl(struct bnxt_qplib_res *res, struct bnxt_qplib_dpi_tbl *dpit) { … } static int bnxt_qplib_alloc_dpi_tbl(struct bnxt_qplib_res *res, struct bnxt_qplib_dev_attr *dev_attr) { … } /* Stats */ static void bnxt_qplib_free_stats_ctx(struct pci_dev *pdev, struct bnxt_qplib_stats *stats) { … } static int bnxt_qplib_alloc_stats_ctx(struct pci_dev *pdev, struct bnxt_qplib_chip_ctx *cctx, struct bnxt_qplib_stats *stats) { … } void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res) { … } int bnxt_qplib_init_res(struct bnxt_qplib_res *res) { … } void bnxt_qplib_free_res(struct bnxt_qplib_res *res) { … } int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, struct net_device *netdev, struct bnxt_qplib_dev_attr *dev_attr) { … } void bnxt_qplib_unmap_db_bar(struct bnxt_qplib_res *res) { … } int bnxt_qplib_map_db_bar(struct bnxt_qplib_res *res) { … } int bnxt_qplib_determine_atomics(struct pci_dev *dev) { … }
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