linux/drivers/clk/mediatek/clk-mtk.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: James Liao <[email protected]>
 */

#ifndef __DRV_CLK_MTK_H
#define __DRV_CLK_MTK_H

#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/types.h>

#include "reset.h"

#define MAX_MUX_GATE_BIT …
#define INVALID_MUX_GATE_BIT …

#define MHZ …

struct platform_device;

/*
 * We need the clock IDs to start from zero but to maintain devicetree
 * backwards compatibility we can't change bindings to start from zero.
 * Only a few platforms are affected, so we solve issues given by the
 * commonized MTK clocks probe function(s) by adding a dummy clock at
 * the beginning where needed.
 */
#define CLK_DUMMY …

extern const struct clk_ops mtk_clk_dummy_ops;
extern const struct mtk_gate_regs cg_regs_dummy;

#define GATE_DUMMY(_id, _name) …

struct mtk_fixed_clk { … };

#define FIXED_CLK(_id, _name, _parent, _rate) …

int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
				struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num,
				   struct clk_hw_onecell_data *clk_data);

struct mtk_fixed_factor { … };

#define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) …

#define FACTOR(_id, _name, _parent, _mult, _div) …

int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
			     struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
				struct clk_hw_onecell_data *clk_data);

struct mtk_composite { … };

#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift,		\
				_width, _gate, _flags, _muxflags) …

/*
 * In case the rate change propagation to parent clocks is undesirable,
 * this macro allows to specify the clock flags manually.
 */
#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,	\
			_gate, _flags) …

/*
 * Unless necessary, all MUX_GATE clocks propagate rate changes to their
 * parent clock by default.
 */
#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) …

#define MUX(_id, _name, _parents, _reg, _shift, _width) …

#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) …

#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg,	\
					_div_width, _div_shift) …

int mtk_clk_register_composites(struct device *dev,
				const struct mtk_composite *mcs, int num,
				void __iomem *base, spinlock_t *lock,
				struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
				   struct clk_hw_onecell_data *clk_data);

struct mtk_clk_divider { … };

#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) …

int mtk_clk_register_dividers(struct device *dev,
			      const struct mtk_clk_divider *mcds, int num,
			      void __iomem *base, spinlock_t *lock,
			      struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num,
				 struct clk_hw_onecell_data *clk_data);

struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
struct clk_hw_onecell_data *mtk_devm_alloc_clk_data(struct device *dev,
						    unsigned int clk_num);
void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data);

struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
			const char *parent_name, void __iomem *reg);
void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw);

struct mtk_clk_desc { … };

int mtk_clk_pdev_probe(struct platform_device *pdev);
void mtk_clk_pdev_remove(struct platform_device *pdev);
int mtk_clk_simple_probe(struct platform_device *pdev);
void mtk_clk_simple_remove(struct platform_device *pdev);

#endif /* __DRV_CLK_MTK_H */