linux/drivers/clk/mediatek/clk-pll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: James Liao <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/container_of.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/slab.h>

#include "clk-pll.h"

#define MHZ …

#define REG_CON0 …
#define REG_CON1 …

#define CON0_BASE_EN …
#define CON0_PWR_ON …
#define CON0_ISO_EN …
#define PCW_CHG_BIT …

#define AUDPLL_TUNER_EN …

/* default 7 bits integer, can be overridden with pcwibits. */
#define INTEGER_BITS …

int mtk_pll_is_prepared(struct clk_hw *hw)
{ … }

static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
		u32 pcw, int postdiv)
{ … }

static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
{ … }

static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
{ … }

static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
		int postdiv)
{ … }

/*
 * mtk_pll_calc_values - calculate good values for a given input frequency.
 * @pll:	The pll
 * @pcw:	The pcw value (output)
 * @postdiv:	The post divider (output)
 * @freq:	The desired target frequency
 * @fin:	The input frequency
 *
 */
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
			 u32 freq, u32 fin)
{ … }

int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		     unsigned long parent_rate)
{ … }

unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{ … }

long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
			unsigned long *prate)
{ … }

int mtk_pll_prepare(struct clk_hw *hw)
{ … }

void mtk_pll_unprepare(struct clk_hw *hw)
{ … }

const struct clk_ops mtk_pll_ops = …;

struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
					const struct mtk_pll_data *data,
					void __iomem *base,
					const struct clk_ops *pll_ops)
{ … }

struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
				    void __iomem *base)
{ … }

void mtk_clk_unregister_pll(struct clk_hw *hw)
{ … }

int mtk_clk_register_plls(struct device_node *node,
			  const struct mtk_pll_data *plls, int num_plls,
			  struct clk_hw_onecell_data *clk_data)
{ … }
EXPORT_SYMBOL_GPL(…);

__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
				   const struct mtk_pll_data *data)
{ … }

void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
			     struct clk_hw_onecell_data *clk_data)
{ … }
EXPORT_SYMBOL_GPL(…);

MODULE_LICENSE(…) …;