// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018 MediaTek Inc. * Author: Owen Chen <[email protected]> */ #include <linux/clk-provider.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/slab.h> #include <linux/mfd/syscon.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include "clk-gate.h" #include "clk-mtk.h" #include "clk-mux.h" #include "clk-pll.h" #include <dt-bindings/clock/mt6765-clk.h> /*fmeter div select 4*/ #define _DIV4_ … static DEFINE_SPINLOCK(mt6765_clk_lock); /* Total 12 subsys */ static void __iomem *cksys_base; static void __iomem *apmixed_base; /* CKSYS */ #define CLK_SCP_CFG_0 … #define CLK_SCP_CFG_1 … /* CG */ #define AP_PLL_CON3 … #define PLLON_CON0 … #define PLLON_CON1 … /* clk cfg update */ #define CLK_CFG_0 … #define CLK_CFG_0_SET … #define CLK_CFG_0_CLR … #define CLK_CFG_1 … #define CLK_CFG_1_SET … #define CLK_CFG_1_CLR … #define CLK_CFG_2 … #define CLK_CFG_2_SET … #define CLK_CFG_2_CLR … #define CLK_CFG_3 … #define CLK_CFG_3_SET … #define CLK_CFG_3_CLR … #define CLK_CFG_4 … #define CLK_CFG_4_SET … #define CLK_CFG_4_CLR … #define CLK_CFG_5 … #define CLK_CFG_5_SET … #define CLK_CFG_5_CLR … #define CLK_CFG_6 … #define CLK_CFG_6_SET … #define CLK_CFG_6_CLR … #define CLK_CFG_7 … #define CLK_CFG_7_SET … #define CLK_CFG_7_CLR … #define CLK_CFG_8 … #define CLK_CFG_8_SET … #define CLK_CFG_8_CLR … #define CLK_CFG_9 … #define CLK_CFG_9_SET … #define CLK_CFG_9_CLR … #define CLK_CFG_10 … #define CLK_CFG_10_SET … #define CLK_CFG_10_CLR … #define CLK_CFG_UPDATE … static const struct mtk_fixed_clk fixed_clks[] = …; static const struct mtk_fixed_factor top_divs[] = …; static const char * const axi_parents[] = …; static const char * const mem_parents[] = …; static const char * const mm_parents[] = …; static const char * const scp_parents[] = …; static const char * const mfg_parents[] = …; static const char * const atb_parents[] = …; static const char * const camtg_parents[] = …; static const char * const uart_parents[] = …; static const char * const spi_parents[] = …; static const char * const msdc5hclk_parents[] = …; static const char * const msdc50_0_parents[] = …; static const char * const msdc30_1_parents[] = …; static const char * const audio_parents[] = …; static const char * const aud_intbus_parents[] = …; static const char * const aud_1_parents[] = …; static const char * const aud_engen1_parents[] = …; static const char * const disp_pwm_parents[] = …; static const char * const sspm_parents[] = …; static const char * const dxcc_parents[] = …; static const char * const usb_top_parents[] = …; static const char * const spm_parents[] = …; static const char * const i2c_parents[] = …; static const char * const pwm_parents[] = …; static const char * const seninf_parents[] = …; static const char * const aes_fde_parents[] = …; static const char * const ulposc_parents[] = …; static const char * const camtm_parents[] = …; #define INVALID_UPDATE_REG … #define INVALID_UPDATE_SHIFT … #define INVALID_MUX_GATE … static const struct mtk_mux top_muxes[] = …; static const struct mtk_gate_regs top0_cg_regs = …; static const struct mtk_gate_regs top1_cg_regs = …; static const struct mtk_gate_regs top2_cg_regs = …; #define GATE_TOP0(_id, _name, _parent, _shift) … #define GATE_TOP1(_id, _name, _parent, _shift) … #define GATE_TOP2(_id, _name, _parent, _shift) … static const struct mtk_gate top_clks[] = …; static const struct mtk_gate_regs ifr2_cg_regs = …; static const struct mtk_gate_regs ifr3_cg_regs = …; static const struct mtk_gate_regs ifr4_cg_regs = …; static const struct mtk_gate_regs ifr5_cg_regs = …; #define GATE_IFR2(_id, _name, _parent, _shift) … #define GATE_IFR3(_id, _name, _parent, _shift) … #define GATE_IFR4(_id, _name, _parent, _shift) … #define GATE_IFR5(_id, _name, _parent, _shift) … static const struct mtk_gate ifr_clks[] = …; /* additional CCF control for mipi26M race condition(disp/camera) */ static const struct mtk_gate_regs apmixed_cg_regs = …; #define GATE_APMIXED(_id, _name, _parent, _shift) … static const struct mtk_gate apmixed_clks[] = …; #define MT6765_PLL_FMAX … #define MT6765_PLL_FMIN … #define CON0_MT6765_RST_BAR … #define PLL_INFO_NULL … #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\ _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) … #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ _pcwibits, _pd_reg, _pd_shift, _tuner_reg, \ _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ _pcw_shift) … \ static const struct mtk_pll_data plls[] = …; static int clk_mt6765_apmixed_probe(struct platform_device *pdev) { … } static int clk_mt6765_top_probe(struct platform_device *pdev) { … } static int clk_mt6765_ifr_probe(struct platform_device *pdev) { … } static const struct of_device_id of_match_clk_mt6765[] = …; MODULE_DEVICE_TABLE(of, of_match_clk_mt6765); static int clk_mt6765_probe(struct platform_device *pdev) { … } static struct platform_driver clk_mt6765_drv = …; static int __init clk_mt6765_init(void) { … } arch_initcall(clk_mt6765_init); MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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