/* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved. */ #ifndef __QCOM_SCM_INT_H #define __QCOM_SCM_INT_H struct device; struct qcom_tzmem_pool; enum qcom_scm_convention { … }; extern enum qcom_scm_convention qcom_scm_convention; #define MAX_QCOM_SCM_ARGS … #define MAX_QCOM_SCM_RETS … enum qcom_scm_arg_types { … }; #define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) … #define QCOM_SCM_ARGS(...) … /** * struct qcom_scm_desc * @arginfo: Metadata describing the arguments in args[] * @args: The array of arguments for the secure syscall */ struct qcom_scm_desc { … }; /** * struct qcom_scm_res * @result: The values returned by the secure syscall */ struct qcom_scm_res { … }; int qcom_scm_wait_for_wq_completion(u32 wq_ctx); int scm_get_wq_ctx(u32 *wq_ctx, u32 *flags, u32 *more_pending); #define SCM_SMC_FNID(s, c) … int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc, enum qcom_scm_convention qcom_convention, struct qcom_scm_res *res, bool atomic); #define scm_smc_call(dev, desc, res, atomic) … #define SCM_LEGACY_FNID(s, c) … int scm_legacy_call_atomic(struct device *dev, const struct qcom_scm_desc *desc, struct qcom_scm_res *res); int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, struct qcom_scm_res *res); struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_BOOT … #define QCOM_SCM_BOOT_SET_ADDR … #define QCOM_SCM_BOOT_TERMINATE_PC … #define QCOM_SCM_BOOT_SDI_CONFIG … #define QCOM_SCM_BOOT_SET_DLOAD_MODE … #define QCOM_SCM_BOOT_SET_ADDR_MC … #define QCOM_SCM_BOOT_SET_REMOTE_STATE … #define QCOM_SCM_FLUSH_FLAG_MASK … #define QCOM_SCM_BOOT_MAX_CPUS … #define QCOM_SCM_BOOT_MC_FLAG_AARCH64 … #define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT … #define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT … #define QCOM_SCM_SVC_PIL … #define QCOM_SCM_PIL_PAS_INIT_IMAGE … #define QCOM_SCM_PIL_PAS_MEM_SETUP … #define QCOM_SCM_PIL_PAS_AUTH_AND_RESET … #define QCOM_SCM_PIL_PAS_SHUTDOWN … #define QCOM_SCM_PIL_PAS_IS_SUPPORTED … #define QCOM_SCM_PIL_PAS_MSS_RESET … #define QCOM_SCM_SVC_IO … #define QCOM_SCM_IO_READ … #define QCOM_SCM_IO_WRITE … #define QCOM_SCM_SVC_INFO … #define QCOM_SCM_INFO_IS_CALL_AVAIL … #define QCOM_SCM_SVC_MP … #define QCOM_SCM_MP_RESTORE_SEC_CFG … #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE … #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT … #define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE … #define QCOM_SCM_MP_VIDEO_VAR … #define QCOM_SCM_MP_ASSIGN … #define QCOM_SCM_MP_SHM_BRIDGE_ENABLE … #define QCOM_SCM_MP_SHM_BRIDGE_DELETE … #define QCOM_SCM_MP_SHM_BRIDGE_CREATE … #define QCOM_SCM_SVC_OCMEM … #define QCOM_SCM_OCMEM_LOCK_CMD … #define QCOM_SCM_OCMEM_UNLOCK_CMD … #define QCOM_SCM_SVC_ES … #define QCOM_SCM_ES_INVALIDATE_ICE_KEY … #define QCOM_SCM_ES_CONFIG_SET_ICE_KEY … #define QCOM_SCM_SVC_HDCP … #define QCOM_SCM_HDCP_INVOKE … #define QCOM_SCM_SVC_LMH … #define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE … #define QCOM_SCM_LMH_LIMIT_DCVSH … #define QCOM_SCM_SVC_SMMU_PROGRAM … #define QCOM_SCM_SMMU_PT_FORMAT … #define QCOM_SCM_SMMU_CONFIG_ERRATA1 … #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL … #define QCOM_SCM_SVC_WAITQ … #define QCOM_SCM_WAITQ_RESUME … #define QCOM_SCM_WAITQ_GET_WQ_CTX … #define QCOM_SCM_SVC_GPU … #define QCOM_SCM_SVC_GPU_INIT_REGS … /* common error codes */ #define QCOM_SCM_V2_EBUSY … #define QCOM_SCM_ENOMEM … #define QCOM_SCM_EOPNOTSUPP … #define QCOM_SCM_EINVAL_ADDR … #define QCOM_SCM_EINVAL_ARG … #define QCOM_SCM_ERROR … #define QCOM_SCM_INTERRUPTED … #define QCOM_SCM_WAITQ_SLEEP … static inline int qcom_scm_remap_error(int err) { … } #endif
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