/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_X86_INTEL_FAMILY_H #define _ASM_X86_INTEL_FAMILY_H /* * "Big Core" Processors (Branded as Core, Xeon, etc...) * * While adding a new CPUID for a new microarchitecture, add a new * group to keep logically sorted out in chronological order. Within * that group keep the CPUID for the variants sorted by model number. * * The defined symbol names have the following form: * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF} * where: * OPTFAMILY Describes the family of CPUs that this belongs to. Default * is assumed to be "_CORE" (and should be omitted). Other values * currently in use are _ATOM and _XEON_PHI * MICROARCH Is the code name for the micro-architecture for this core. * N.B. Not the platform name. * OPTDIFF If needed, a short string to differentiate by market segment. * * Common OPTDIFFs: * * - regular client parts * _L - regular mobile parts * _G - parts with extra graphics on * _X - regular server parts * _D - micro server parts * _N,_P - other mobile parts * _H - premium mobile parts * _S - other client parts * * Historical OPTDIFFs: * * _EP - 2 socket server parts * _EX - 4+ socket server parts * * The #define line may optionally include a comment including platform or core * names. An exception is made for skylake/kabylake where steppings seem to have gotten * their own names :-( */ #define IFM(_fam, _model) … /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */ #define INTEL_FAM6_ANY … /* Wildcard match for FAM6 so X86_MATCH_VFM(ANY) works */ #define INTEL_ANY … #define INTEL_FAM6_CORE_YONAH … #define INTEL_CORE_YONAH … #define INTEL_FAM6_CORE2_MEROM … #define INTEL_CORE2_MEROM … #define INTEL_FAM6_CORE2_MEROM_L … #define INTEL_CORE2_MEROM_L … #define INTEL_FAM6_CORE2_PENRYN … #define INTEL_CORE2_PENRYN … #define INTEL_FAM6_CORE2_DUNNINGTON … #define INTEL_CORE2_DUNNINGTON … #define INTEL_FAM6_NEHALEM … #define INTEL_NEHALEM … #define INTEL_FAM6_NEHALEM_G … #define INTEL_NEHALEM_G … #define INTEL_FAM6_NEHALEM_EP … #define INTEL_NEHALEM_EP … #define INTEL_FAM6_NEHALEM_EX … #define INTEL_NEHALEM_EX … #define INTEL_FAM6_WESTMERE … #define INTEL_WESTMERE … #define INTEL_FAM6_WESTMERE_EP … #define INTEL_WESTMERE_EP … #define INTEL_FAM6_WESTMERE_EX … #define INTEL_WESTMERE_EX … #define INTEL_FAM6_SANDYBRIDGE … #define INTEL_SANDYBRIDGE … #define INTEL_FAM6_SANDYBRIDGE_X … #define INTEL_SANDYBRIDGE_X … #define INTEL_FAM6_IVYBRIDGE … #define INTEL_IVYBRIDGE … #define INTEL_FAM6_IVYBRIDGE_X … #define INTEL_IVYBRIDGE_X … #define INTEL_FAM6_HASWELL … #define INTEL_HASWELL … #define INTEL_FAM6_HASWELL_X … #define INTEL_HASWELL_X … #define INTEL_FAM6_HASWELL_L … #define INTEL_HASWELL_L … #define INTEL_FAM6_HASWELL_G … #define INTEL_HASWELL_G … #define INTEL_FAM6_BROADWELL … #define INTEL_BROADWELL … #define INTEL_FAM6_BROADWELL_G … #define INTEL_BROADWELL_G … #define INTEL_FAM6_BROADWELL_X … #define INTEL_BROADWELL_X … #define INTEL_FAM6_BROADWELL_D … #define INTEL_BROADWELL_D … #define INTEL_FAM6_SKYLAKE_L … #define INTEL_SKYLAKE_L … #define INTEL_FAM6_SKYLAKE … #define INTEL_SKYLAKE … #define INTEL_FAM6_SKYLAKE_X … #define INTEL_SKYLAKE_X … /* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */ /* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */ #define INTEL_FAM6_KABYLAKE_L … #define INTEL_KABYLAKE_L … /* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */ /* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */ /* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */ #define INTEL_FAM6_KABYLAKE … #define INTEL_KABYLAKE … /* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */ #define INTEL_FAM6_COMETLAKE … #define INTEL_COMETLAKE … #define INTEL_FAM6_COMETLAKE_L … #define INTEL_COMETLAKE_L … #define INTEL_FAM6_CANNONLAKE_L … #define INTEL_CANNONLAKE_L … #define INTEL_FAM6_ICELAKE_X … #define INTEL_ICELAKE_X … #define INTEL_FAM6_ICELAKE_D … #define INTEL_ICELAKE_D … #define INTEL_FAM6_ICELAKE … #define INTEL_ICELAKE … #define INTEL_FAM6_ICELAKE_L … #define INTEL_ICELAKE_L … #define INTEL_FAM6_ICELAKE_NNPI … #define INTEL_ICELAKE_NNPI … #define INTEL_FAM6_ROCKETLAKE … #define INTEL_ROCKETLAKE … #define INTEL_FAM6_TIGERLAKE_L … #define INTEL_TIGERLAKE_L … #define INTEL_FAM6_TIGERLAKE … #define INTEL_TIGERLAKE … #define INTEL_FAM6_SAPPHIRERAPIDS_X … #define INTEL_SAPPHIRERAPIDS_X … #define INTEL_FAM6_EMERALDRAPIDS_X … #define INTEL_EMERALDRAPIDS_X … #define INTEL_FAM6_GRANITERAPIDS_X … #define INTEL_GRANITERAPIDS_X … #define INTEL_FAM6_GRANITERAPIDS_D … #define INTEL_GRANITERAPIDS_D … /* "Hybrid" Processors (P-Core/E-Core) */ #define INTEL_FAM6_LAKEFIELD … #define INTEL_LAKEFIELD … #define INTEL_FAM6_ALDERLAKE … #define INTEL_ALDERLAKE … #define INTEL_FAM6_ALDERLAKE_L … #define INTEL_ALDERLAKE_L … #define INTEL_FAM6_RAPTORLAKE … #define INTEL_RAPTORLAKE … #define INTEL_FAM6_RAPTORLAKE_P … #define INTEL_RAPTORLAKE_P … #define INTEL_FAM6_RAPTORLAKE_S … #define INTEL_RAPTORLAKE_S … #define INTEL_FAM6_METEORLAKE … #define INTEL_METEORLAKE … #define INTEL_FAM6_METEORLAKE_L … #define INTEL_METEORLAKE_L … #define INTEL_FAM6_ARROWLAKE_H … #define INTEL_ARROWLAKE_H … #define INTEL_FAM6_ARROWLAKE … #define INTEL_ARROWLAKE … #define INTEL_FAM6_ARROWLAKE_U … #define INTEL_ARROWLAKE_U … #define INTEL_FAM6_LUNARLAKE_M … #define INTEL_LUNARLAKE_M … /* "Small Core" Processors (Atom/E-Core) */ #define INTEL_FAM6_ATOM_BONNELL … #define INTEL_ATOM_BONNELL … #define INTEL_FAM6_ATOM_BONNELL_MID … #define INTEL_ATOM_BONNELL_MID … #define INTEL_FAM6_ATOM_SALTWELL … #define INTEL_ATOM_SALTWELL … #define INTEL_FAM6_ATOM_SALTWELL_MID … #define INTEL_ATOM_SALTWELL_MID … #define INTEL_FAM6_ATOM_SALTWELL_TABLET … #define INTEL_ATOM_SALTWELL_TABLET … #define INTEL_FAM6_ATOM_SILVERMONT … #define INTEL_ATOM_SILVERMONT … #define INTEL_FAM6_ATOM_SILVERMONT_D … #define INTEL_ATOM_SILVERMONT_D … #define INTEL_FAM6_ATOM_SILVERMONT_MID … #define INTEL_ATOM_SILVERMONT_MID … #define INTEL_FAM6_ATOM_AIRMONT … #define INTEL_ATOM_AIRMONT … #define INTEL_FAM6_ATOM_AIRMONT_MID … #define INTEL_ATOM_AIRMONT_MID … #define INTEL_FAM6_ATOM_AIRMONT_NP … #define INTEL_ATOM_AIRMONT_NP … #define INTEL_FAM6_ATOM_GOLDMONT … #define INTEL_ATOM_GOLDMONT … #define INTEL_FAM6_ATOM_GOLDMONT_D … #define INTEL_ATOM_GOLDMONT_D … /* Note: the micro-architecture is "Goldmont Plus" */ #define INTEL_FAM6_ATOM_GOLDMONT_PLUS … #define INTEL_ATOM_GOLDMONT_PLUS … #define INTEL_FAM6_ATOM_TREMONT_D … #define INTEL_ATOM_TREMONT_D … #define INTEL_FAM6_ATOM_TREMONT … #define INTEL_ATOM_TREMONT … #define INTEL_FAM6_ATOM_TREMONT_L … #define INTEL_ATOM_TREMONT_L … #define INTEL_FAM6_ATOM_GRACEMONT … #define INTEL_ATOM_GRACEMONT … #define INTEL_FAM6_ATOM_CRESTMONT_X … #define INTEL_ATOM_CRESTMONT_X … #define INTEL_FAM6_ATOM_CRESTMONT … #define INTEL_ATOM_CRESTMONT … #define INTEL_FAM6_ATOM_DARKMONT_X … #define INTEL_ATOM_DARKMONT_X … /* Xeon Phi */ #define INTEL_FAM6_XEON_PHI_KNL … #define INTEL_XEON_PHI_KNL … #define INTEL_FAM6_XEON_PHI_KNM … #define INTEL_XEON_PHI_KNM … /* Family 5 */ #define INTEL_FAM5_QUARK_X1000 … #define INTEL_QUARK_X1000 … #endif /* _ASM_X86_INTEL_FAMILY_H */
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