/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2019 MediaTek Inc. * Author: Wendell Lin <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT6779_H #define _DT_BINDINGS_CLK_MT6779_H /* TOPCKGEN */ #define CLK_TOP_AXI … #define CLK_TOP_MM … #define CLK_TOP_CAM … #define CLK_TOP_MFG … #define CLK_TOP_CAMTG … #define CLK_TOP_UART … #define CLK_TOP_SPI … #define CLK_TOP_MSDC50_0_HCLK … #define CLK_TOP_MSDC50_0 … #define CLK_TOP_MSDC30_1 … #define CLK_TOP_MSDC30_2 … #define CLK_TOP_AUD … #define CLK_TOP_AUD_INTBUS … #define CLK_TOP_FPWRAP_ULPOSC … #define CLK_TOP_SCP … #define CLK_TOP_ATB … #define CLK_TOP_SSPM … #define CLK_TOP_DPI0 … #define CLK_TOP_SCAM … #define CLK_TOP_AUD_1 … #define CLK_TOP_AUD_2 … #define CLK_TOP_DISP_PWM … #define CLK_TOP_SSUSB_TOP_XHCI … #define CLK_TOP_USB_TOP … #define CLK_TOP_SPM … #define CLK_TOP_I2C … #define CLK_TOP_F52M_MFG … #define CLK_TOP_SENINF … #define CLK_TOP_DXCC … #define CLK_TOP_CAMTG2 … #define CLK_TOP_AUD_ENG1 … #define CLK_TOP_AUD_ENG2 … #define CLK_TOP_FAES_UFSFDE … #define CLK_TOP_FUFS … #define CLK_TOP_IMG … #define CLK_TOP_DSP … #define CLK_TOP_DSP1 … #define CLK_TOP_DSP2 … #define CLK_TOP_IPU_IF … #define CLK_TOP_CAMTG3 … #define CLK_TOP_CAMTG4 … #define CLK_TOP_PMICSPI … #define CLK_TOP_MAINPLL_CK … #define CLK_TOP_MAINPLL_D2 … #define CLK_TOP_MAINPLL_D3 … #define CLK_TOP_MAINPLL_D5 … #define CLK_TOP_MAINPLL_D7 … #define CLK_TOP_MAINPLL_D2_D2 … #define CLK_TOP_MAINPLL_D2_D4 … #define CLK_TOP_MAINPLL_D2_D8 … #define CLK_TOP_MAINPLL_D2_D16 … #define CLK_TOP_MAINPLL_D3_D2 … #define CLK_TOP_MAINPLL_D3_D4 … #define CLK_TOP_MAINPLL_D3_D8 … #define CLK_TOP_MAINPLL_D5_D2 … #define CLK_TOP_MAINPLL_D5_D4 … #define CLK_TOP_MAINPLL_D7_D2 … #define CLK_TOP_MAINPLL_D7_D4 … #define CLK_TOP_UNIVPLL_CK … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_D2_D2 … #define CLK_TOP_UNIVPLL_D2_D4 … #define CLK_TOP_UNIVPLL_D2_D8 … #define CLK_TOP_UNIVPLL_D3_D2 … #define CLK_TOP_UNIVPLL_D3_D4 … #define CLK_TOP_UNIVPLL_D3_D8 … #define CLK_TOP_UNIVPLL_D5_D2 … #define CLK_TOP_UNIVPLL_D5_D4 … #define CLK_TOP_UNIVPLL_D5_D8 … #define CLK_TOP_APLL1_CK … #define CLK_TOP_APLL1_D2 … #define CLK_TOP_APLL1_D4 … #define CLK_TOP_APLL1_D8 … #define CLK_TOP_APLL2_CK … #define CLK_TOP_APLL2_D2 … #define CLK_TOP_APLL2_D4 … #define CLK_TOP_APLL2_D8 … #define CLK_TOP_TVDPLL_CK … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_MSDCPLL_CK … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D4 … #define CLK_TOP_MSDCPLL_D8 … #define CLK_TOP_MSDCPLL_D16 … #define CLK_TOP_AD_OSC_CK … #define CLK_TOP_OSC_D2 … #define CLK_TOP_OSC_D4 … #define CLK_TOP_OSC_D8 … #define CLK_TOP_OSC_D16 … #define CLK_TOP_F26M_CK_D2 … #define CLK_TOP_MFGPLL_CK … #define CLK_TOP_UNIVP_192M_CK … #define CLK_TOP_UNIVP_192M_D2 … #define CLK_TOP_UNIVP_192M_D4 … #define CLK_TOP_UNIVP_192M_D8 … #define CLK_TOP_UNIVP_192M_D16 … #define CLK_TOP_UNIVP_192M_D32 … #define CLK_TOP_MMPLL_CK … #define CLK_TOP_MMPLL_D4 … #define CLK_TOP_MMPLL_D4_D2 … #define CLK_TOP_MMPLL_D4_D4 … #define CLK_TOP_MMPLL_D5 … #define CLK_TOP_MMPLL_D5_D2 … #define CLK_TOP_MMPLL_D5_D4 … #define CLK_TOP_MMPLL_D6 … #define CLK_TOP_MMPLL_D7 … #define CLK_TOP_CLK26M … #define CLK_TOP_CLK13M … #define CLK_TOP_ADSP … #define CLK_TOP_DPMAIF … #define CLK_TOP_VENC … #define CLK_TOP_VDEC … #define CLK_TOP_CAMTM … #define CLK_TOP_PWM … #define CLK_TOP_ADSPPLL_CK … #define CLK_TOP_I2S0_M_SEL … #define CLK_TOP_I2S1_M_SEL … #define CLK_TOP_I2S2_M_SEL … #define CLK_TOP_I2S3_M_SEL … #define CLK_TOP_I2S4_M_SEL … #define CLK_TOP_I2S5_M_SEL … #define CLK_TOP_APLL12_DIV0 … #define CLK_TOP_APLL12_DIV1 … #define CLK_TOP_APLL12_DIV2 … #define CLK_TOP_APLL12_DIV3 … #define CLK_TOP_APLL12_DIV4 … #define CLK_TOP_APLL12_DIVB … #define CLK_TOP_APLL12_DIV5 … #define CLK_TOP_IPE … #define CLK_TOP_DPE … #define CLK_TOP_CCU … #define CLK_TOP_DSP3 … #define CLK_TOP_SENINF1 … #define CLK_TOP_SENINF2 … #define CLK_TOP_AUD_H … #define CLK_TOP_CAMTG5 … #define CLK_TOP_TVDPLL_MAINPLL_D2_CK … #define CLK_TOP_AD_OSC2_CK … #define CLK_TOP_OSC2_D2 … #define CLK_TOP_OSC2_D3 … #define CLK_TOP_FMEM_466M_CK … #define CLK_TOP_ADSPPLL_D4 … #define CLK_TOP_ADSPPLL_D5 … #define CLK_TOP_ADSPPLL_D6 … #define CLK_TOP_OSC_D10 … #define CLK_TOP_UNIVPLL_D3_D16 … #define CLK_TOP_NR_CLK … /* APMIXED */ #define CLK_APMIXED_ARMPLL_LL … #define CLK_APMIXED_ARMPLL_BL … #define CLK_APMIXED_ARMPLL_BB … #define CLK_APMIXED_CCIPLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIV2PLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_ADSPPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_MFGPLL … #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_SSUSB26M … #define CLK_APMIXED_APPLL26M … #define CLK_APMIXED_MIPIC0_26M … #define CLK_APMIXED_MDPLLGP26M … #define CLK_APMIXED_MM_F26M … #define CLK_APMIXED_UFS26M … #define CLK_APMIXED_MIPIC1_26M … #define CLK_APMIXED_MEMPLL26M … #define CLK_APMIXED_CLKSQ_LVPLL_26M … #define CLK_APMIXED_MIPID0_26M … #define CLK_APMIXED_MIPID1_26M … #define CLK_APMIXED_NR_CLK … /* CAMSYS */ #define CLK_CAM_LARB10 … #define CLK_CAM_DFP_VAD … #define CLK_CAM_LARB11 … #define CLK_CAM_LARB9 … #define CLK_CAM_CAM … #define CLK_CAM_CAMTG … #define CLK_CAM_SENINF … #define CLK_CAM_CAMSV0 … #define CLK_CAM_CAMSV1 … #define CLK_CAM_CAMSV2 … #define CLK_CAM_CAMSV3 … #define CLK_CAM_CCU … #define CLK_CAM_FAKE_ENG … #define CLK_CAM_NR_CLK … /* INFRA */ #define CLK_INFRA_PMIC_TMR … #define CLK_INFRA_PMIC_AP … #define CLK_INFRA_PMIC_MD … #define CLK_INFRA_PMIC_CONN … #define CLK_INFRA_SCPSYS … #define CLK_INFRA_SEJ … #define CLK_INFRA_APXGPT … #define CLK_INFRA_ICUSB … #define CLK_INFRA_GCE … #define CLK_INFRA_THERM … #define CLK_INFRA_I2C0 … #define CLK_INFRA_I2C1 … #define CLK_INFRA_I2C2 … #define CLK_INFRA_I2C3 … #define CLK_INFRA_PWM_HCLK … #define CLK_INFRA_PWM1 … #define CLK_INFRA_PWM2 … #define CLK_INFRA_PWM3 … #define CLK_INFRA_PWM4 … #define CLK_INFRA_PWM … #define CLK_INFRA_UART0 … #define CLK_INFRA_UART1 … #define CLK_INFRA_UART2 … #define CLK_INFRA_UART3 … #define CLK_INFRA_GCE_26M … #define CLK_INFRA_CQ_DMA_FPC … #define CLK_INFRA_BTIF … #define CLK_INFRA_SPI0 … #define CLK_INFRA_MSDC0 … #define CLK_INFRA_MSDC1 … #define CLK_INFRA_MSDC2 … #define CLK_INFRA_MSDC0_SCK … #define CLK_INFRA_DVFSRC … #define CLK_INFRA_GCPU … #define CLK_INFRA_TRNG … #define CLK_INFRA_AUXADC … #define CLK_INFRA_CPUM … #define CLK_INFRA_CCIF1_AP … #define CLK_INFRA_CCIF1_MD … #define CLK_INFRA_AUXADC_MD … #define CLK_INFRA_MSDC1_SCK … #define CLK_INFRA_MSDC2_SCK … #define CLK_INFRA_AP_DMA … #define CLK_INFRA_XIU … #define CLK_INFRA_DEVICE_APC … #define CLK_INFRA_CCIF_AP … #define CLK_INFRA_DEBUGSYS … #define CLK_INFRA_AUD … #define CLK_INFRA_CCIF_MD … #define CLK_INFRA_DXCC_SEC_CORE … #define CLK_INFRA_DXCC_AO … #define CLK_INFRA_DRAMC_F26M … #define CLK_INFRA_IRTX … #define CLK_INFRA_DISP_PWM … #define CLK_INFRA_DPMAIF_CK … #define CLK_INFRA_AUD_26M_BCLK … #define CLK_INFRA_SPI1 … #define CLK_INFRA_I2C4 … #define CLK_INFRA_MODEM_TEMP_SHARE … #define CLK_INFRA_SPI2 … #define CLK_INFRA_SPI3 … #define CLK_INFRA_UNIPRO_SCK … #define CLK_INFRA_UNIPRO_TICK … #define CLK_INFRA_UFS_MP_SAP_BCLK … #define CLK_INFRA_MD32_BCLK … #define CLK_INFRA_SSPM … #define CLK_INFRA_UNIPRO_MBIST … #define CLK_INFRA_SSPM_BUS_HCLK … #define CLK_INFRA_I2C5 … #define CLK_INFRA_I2C5_ARBITER … #define CLK_INFRA_I2C5_IMM … #define CLK_INFRA_I2C1_ARBITER … #define CLK_INFRA_I2C1_IMM … #define CLK_INFRA_I2C2_ARBITER … #define CLK_INFRA_I2C2_IMM … #define CLK_INFRA_SPI4 … #define CLK_INFRA_SPI5 … #define CLK_INFRA_CQ_DMA … #define CLK_INFRA_UFS … #define CLK_INFRA_AES_UFSFDE … #define CLK_INFRA_UFS_TICK … #define CLK_INFRA_MSDC0_SELF … #define CLK_INFRA_MSDC1_SELF … #define CLK_INFRA_MSDC2_SELF … #define CLK_INFRA_SSPM_26M_SELF … #define CLK_INFRA_SSPM_32K_SELF … #define CLK_INFRA_UFS_AXI … #define CLK_INFRA_I2C6 … #define CLK_INFRA_AP_MSDC0 … #define CLK_INFRA_MD_MSDC0 … #define CLK_INFRA_USB … #define CLK_INFRA_DEVMPU_BCLK … #define CLK_INFRA_CCIF2_AP … #define CLK_INFRA_CCIF2_MD … #define CLK_INFRA_CCIF3_AP … #define CLK_INFRA_CCIF3_MD … #define CLK_INFRA_SEJ_F13M … #define CLK_INFRA_AES_BCLK … #define CLK_INFRA_I2C7 … #define CLK_INFRA_I2C8 … #define CLK_INFRA_FBIST2FPC … #define CLK_INFRA_CCIF4_AP … #define CLK_INFRA_CCIF4_MD … #define CLK_INFRA_FADSP … #define CLK_INFRA_SSUSB_XHCI … #define CLK_INFRA_SPI6 … #define CLK_INFRA_SPI7 … #define CLK_INFRA_NR_CLK … /* MFGCFG */ #define CLK_MFGCFG_BG3D … #define CLK_MFGCFG_NR_CLK … /* IMG */ #define CLK_IMG_WPE_A … #define CLK_IMG_MFB … #define CLK_IMG_DIP … #define CLK_IMG_LARB6 … #define CLK_IMG_LARB5 … #define CLK_IMG_NR_CLK … /* IPE */ #define CLK_IPE_LARB7 … #define CLK_IPE_LARB8 … #define CLK_IPE_SMI_SUBCOM … #define CLK_IPE_FD … #define CLK_IPE_FE … #define CLK_IPE_RSC … #define CLK_IPE_DPE … #define CLK_IPE_NR_CLK … /* MM_CONFIG */ #define CLK_MM_SMI_COMMON … #define CLK_MM_SMI_LARB0 … #define CLK_MM_SMI_LARB1 … #define CLK_MM_GALS_COMM0 … #define CLK_MM_GALS_COMM1 … #define CLK_MM_GALS_CCU2MM … #define CLK_MM_GALS_IPU12MM … #define CLK_MM_GALS_IMG2MM … #define CLK_MM_GALS_CAM2MM … #define CLK_MM_GALS_IPU2MM … #define CLK_MM_MDP_DL_TXCK … #define CLK_MM_IPU_DL_TXCK … #define CLK_MM_MDP_RDMA0 … #define CLK_MM_MDP_RDMA1 … #define CLK_MM_MDP_RSZ0 … #define CLK_MM_MDP_RSZ1 … #define CLK_MM_MDP_TDSHP … #define CLK_MM_MDP_WROT0 … #define CLK_MM_FAKE_ENG … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_OVL0_2L … #define CLK_MM_DISP_OVL1_2L … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_RDMA1 … #define CLK_MM_DISP_WDMA0 … #define CLK_MM_DISP_COLOR0 … #define CLK_MM_DISP_CCORR0 … #define CLK_MM_DISP_AAL0 … #define CLK_MM_DISP_GAMMA0 … #define CLK_MM_DISP_DITHER0 … #define CLK_MM_DISP_SPLIT … #define CLK_MM_DSI0_MM_CK … #define CLK_MM_DSI0_IF_CK … #define CLK_MM_DPI_MM_CK … #define CLK_MM_DPI_IF_CK … #define CLK_MM_FAKE_ENG2 … #define CLK_MM_MDP_DL_RX_CK … #define CLK_MM_IPU_DL_RX_CK … #define CLK_MM_26M … #define CLK_MM_MM_R2Y … #define CLK_MM_DISP_RSZ … #define CLK_MM_MDP_WDMA0 … #define CLK_MM_MDP_AAL … #define CLK_MM_MDP_HDR … #define CLK_MM_DBI_MM_CK … #define CLK_MM_DBI_IF_CK … #define CLK_MM_MDP_WROT1 … #define CLK_MM_DISP_POSTMASK0 … #define CLK_MM_DISP_HRT_BW … #define CLK_MM_DISP_OVL_FBDC … #define CLK_MM_NR_CLK … /* VDEC_GCON */ #define CLK_VDEC_VDEC … #define CLK_VDEC_LARB1 … #define CLK_VDEC_GCON_NR_CLK … /* VENC_GCON */ #define CLK_VENC_GCON_LARB … #define CLK_VENC_GCON_VENC … #define CLK_VENC_GCON_JPGENC … #define CLK_VENC_GCON_GALS … #define CLK_VENC_GCON_NR_CLK … /* AUD */ #define CLK_AUD_AFE … #define CLK_AUD_22M … #define CLK_AUD_24M … #define CLK_AUD_APLL2_TUNER … #define CLK_AUD_APLL_TUNER … #define CLK_AUD_TDM … #define CLK_AUD_ADC … #define CLK_AUD_DAC … #define CLK_AUD_DAC_PREDIS … #define CLK_AUD_TML … #define CLK_AUD_NLE … #define CLK_AUD_I2S1_BCLK_SW … #define CLK_AUD_I2S2_BCLK_SW … #define CLK_AUD_I2S3_BCLK_SW … #define CLK_AUD_I2S4_BCLK_SW … #define CLK_AUD_I2S5_BCLK_SW … #define CLK_AUD_CONN_I2S_ASRC … #define CLK_AUD_GENERAL1_ASRC … #define CLK_AUD_GENERAL2_ASRC … #define CLK_AUD_DAC_HIRES … #define CLK_AUD_PDN_ADDA6_ADC … #define CLK_AUD_ADC_HIRES … #define CLK_AUD_ADC_HIRES_TML … #define CLK_AUD_ADDA6_ADC_HIRES … #define CLK_AUD_3RD_DAC … #define CLK_AUD_3RD_DAC_PREDIS … #define CLK_AUD_3RD_DAC_TML … #define CLK_AUD_3RD_DAC_HIRES … #define CLK_AUD_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT6779_H */
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