/***********************license start************************************ * Copyright (c) 2003-2017 Cavium, Inc. * All rights reserved. * * License: one of 'Cavium License' or 'GNU General Public License Version 2' * * This file is provided under the terms of the Cavium License (see below) * or under the terms of GNU General Public License, Version 2, as * published by the Free Software Foundation. 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THE * ENTIRE RISK ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES * WITH YOU. ***********************license end**************************************/ #ifndef __ZIP_REGS_H__ #define __ZIP_REGS_H__ /* * Configuration and status register (CSR) address and type definitions for * Cavium ZIP. */ #include <linux/kern_levels.h> /* ZIP invocation result completion status codes */ #define ZIP_CMD_NOTDONE … /* Successful completion. */ #define ZIP_CMD_SUCCESS … /* Output truncated */ #define ZIP_CMD_DTRUNC … /* Dynamic Stop */ #define ZIP_CMD_DYNAMIC_STOP … /* Uncompress ran out of input data when IWORD0[EF] was set */ #define ZIP_CMD_ITRUNC … /* Uncompress found the reserved block type 3 */ #define ZIP_CMD_RBLOCK … /* * Uncompress found LEN != ZIP_CMD_NLEN in an uncompressed block in the input. */ #define ZIP_CMD_NLEN … /* Uncompress found a bad code in the main Huffman codes. */ #define ZIP_CMD_BADCODE … /* Uncompress found a bad code in the 19 Huffman codes encoding lengths. */ #define ZIP_CMD_BADCODE2 … /* Compress found a zero-length input. */ #define ZIP_CMD_ZERO_LEN … /* The compress or decompress encountered an internal parity error. */ #define ZIP_CMD_PARITY … /* * Uncompress found a string identifier that precedes the uncompressed data and * decompression history. */ #define ZIP_CMD_FATAL … /** * enum zip_int_vec_e - ZIP MSI-X Vector Enumeration, enumerates the MSI-X * interrupt vectors. */ enum zip_int_vec_e { … }; /** * union zip_zptr_addr_s - ZIP Generic Pointer Structure for ADDR. * * It is the generic format of pointers in ZIP_INST_S. */ zip_zptr_addr_s; /** * union zip_zptr_ctl_s - ZIP Generic Pointer Structure for CTL. * * It is the generic format of pointers in ZIP_INST_S. */ zip_zptr_ctl_s; /** * union zip_inst_s - ZIP Instruction Structure. * Each ZIP instruction has 16 words (they are called IWORD0 to IWORD15 within * the structure). */ zip_inst_s; /** * union zip_nptr_s - ZIP Instruction Next-Chunk-Buffer Pointer (NPTR) * Structure * * ZIP_NPTR structure is used to chain all the zip instruction buffers * together. ZIP instruction buffers are managed (allocated and released) by * the software. */ zip_nptr_s; /** * union zip_zptr_s - ZIP Generic Pointer Structure. * * It is the generic format of pointers in ZIP_INST_S. */ zip_zptr_s; /** * union zip_zres_s - ZIP Result Structure * * The ZIP coprocessor writes the result structure after it completes the * invocation. The result structure is exactly 24 bytes, and each invocation of * the ZIP coprocessor produces exactly one result structure. */ zip_zres_s; /** * union zip_cmd_ctl - Structure representing the register that controls * clock and reset. */ zip_cmd_ctl; #define ZIP_CMD_CTL … /** * union zip_constants - Data structure representing the register that contains * all of the current implementation-related parameters of the zip core in this * chip. */ zip_constants; #define ZIP_CONSTANTS … /** * union zip_corex_bist_status - Represents registers which have the BIST * status of memories in zip cores. * * Each bit is the BIST result of an individual memory * (per bit, 0 = pass and 1 = fail). */ zip_corex_bist_status; static inline u64 ZIP_COREX_BIST_STATUS(u64 param1) { … } /** * union zip_ctl_bist_status - Represents register that has the BIST status of * memories in ZIP_CTL (instruction buffer, G/S pointer FIFO, input data * buffer, output data buffers). * * Each bit is the BIST result of an individual memory * (per bit, 0 = pass and 1 = fail). */ zip_ctl_bist_status; #define ZIP_CTL_BIST_STATUS … /** * union zip_ctl_cfg - Represents the register that controls the behavior of * the ZIP DMA engines. * * It is recommended to keep default values for normal operation. Changing the * values of the fields may be useful for diagnostics. */ zip_ctl_cfg; #define ZIP_CTL_CFG … /** * union zip_dbg_corex_inst - Represents the registers that reflect the status * of the current instruction that the ZIP core is executing or has executed. * * These registers are only for debug use. */ zip_dbg_corex_inst; static inline u64 ZIP_DBG_COREX_INST(u64 param1) { … } /** * union zip_dbg_corex_sta - Represents registers that reflect the status of * the zip cores. * * They are for debug use only. */ zip_dbg_corex_sta; static inline u64 ZIP_DBG_COREX_STA(u64 param1) { … } /** * union zip_dbg_quex_sta - Represets registers that reflect status of the zip * instruction queues. * * They are for debug use only. */ zip_dbg_quex_sta; static inline u64 ZIP_DBG_QUEX_STA(u64 param1) { … } /** * union zip_ecc_ctl - Represents the register that enables ECC for each * individual internal memory that requires ECC. * * For debug purpose, it can also flip one or two bits in the ECC data. */ zip_ecc_ctl; #define ZIP_ECC_CTL … /* NCB - zip_ecce_ena_w1c */ zip_ecce_ena_w1c; #define ZIP_ECCE_ENA_W1C … /* NCB - zip_ecce_ena_w1s */ zip_ecce_ena_w1s; #define ZIP_ECCE_ENA_W1S … /** * union zip_ecce_int - Represents the register that contains the status of the * ECC interrupt sources. */ zip_ecce_int; #define ZIP_ECCE_INT … /* NCB - zip_ecce_int_w1s */ zip_ecce_int_w1s; #define ZIP_ECCE_INT_W1S … /* NCB - zip_fife_ena_w1c */ zip_fife_ena_w1c; #define ZIP_FIFE_ENA_W1C … /* NCB - zip_fife_ena_w1s */ zip_fife_ena_w1s; #define ZIP_FIFE_ENA_W1S … /* NCB - zip_fife_int */ zip_fife_int; #define ZIP_FIFE_INT … /* NCB - zip_fife_int_w1s */ zip_fife_int_w1s; #define ZIP_FIFE_INT_W1S … /** * union zip_msix_pbax - Represents the register that is the MSI-X PBA table * * The bit number is indexed by the ZIP_INT_VEC_E enumeration. */ zip_msix_pbax; static inline u64 ZIP_MSIX_PBAX(u64 param1) { … } /** * union zip_msix_vecx_addr - Represents the register that is the MSI-X vector * table, indexed by the ZIP_INT_VEC_E enumeration. */ zip_msix_vecx_addr; static inline u64 ZIP_MSIX_VECX_ADDR(u64 param1) { … } /** * union zip_msix_vecx_ctl - Represents the register that is the MSI-X vector * table, indexed by the ZIP_INT_VEC_E enumeration. */ zip_msix_vecx_ctl; static inline u64 ZIP_MSIX_VECX_CTL(u64 param1) { … } /** * union zip_quex_done - Represents the registers that contain the per-queue * instruction done count. */ zip_quex_done; static inline u64 ZIP_QUEX_DONE(u64 param1) { … } /** * union zip_quex_done_ack - Represents the registers on write to which will * decrement the per-queue instructiona done count. */ zip_quex_done_ack; static inline u64 ZIP_QUEX_DONE_ACK(u64 param1) { … } /** * union zip_quex_done_ena_w1c - Represents the register which when written * 1 to will disable the DONEINT interrupt for the queue. */ zip_quex_done_ena_w1c; static inline u64 ZIP_QUEX_DONE_ENA_W1C(u64 param1) { … } /** * union zip_quex_done_ena_w1s - Represents the register that when written 1 to * will enable the DONEINT interrupt for the queue. */ zip_quex_done_ena_w1s; static inline u64 ZIP_QUEX_DONE_ENA_W1S(u64 param1) { … } /** * union zip_quex_done_wait - Represents the register that specifies the per * queue interrupt coalescing settings. */ zip_quex_done_wait; static inline u64 ZIP_QUEX_DONE_WAIT(u64 param1) { … } /** * union zip_quex_doorbell - Represents doorbell registers for the ZIP * instruction queues. */ zip_quex_doorbell; static inline u64 ZIP_QUEX_DOORBELL(u64 param1) { … } zip_quex_err_ena_w1c; static inline u64 ZIP_QUEX_ERR_ENA_W1C(u64 param1) { … } zip_quex_err_ena_w1s; static inline u64 ZIP_QUEX_ERR_ENA_W1S(u64 param1) { … } /** * union zip_quex_err_int - Represents registers that contain the per-queue * error interrupts. */ zip_quex_err_int; static inline u64 ZIP_QUEX_ERR_INT(u64 param1) { … } /* NCB - zip_que#_err_int_w1s */ zip_quex_err_int_w1s; static inline u64 ZIP_QUEX_ERR_INT_W1S(u64 param1) { … } /** * union zip_quex_gcfg - Represents the registers that reflect status of the * zip instruction queues,debug use only. */ zip_quex_gcfg; static inline u64 ZIP_QUEX_GCFG(u64 param1) { … } /** * union zip_quex_map - Represents the registers that control how each * instruction queue maps to zip cores. */ zip_quex_map; static inline u64 ZIP_QUEX_MAP(u64 param1) { … } /** * union zip_quex_sbuf_addr - Represents the registers that set the buffer * parameters for the instruction queues. * * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite * this register to effectively reset the command buffer state machine. * These registers must be programmed after SW programs the corresponding * ZIP_QUE(0..7)_SBUF_CTL. */ zip_quex_sbuf_addr; static inline u64 ZIP_QUEX_SBUF_ADDR(u64 param1) { … } /** * union zip_quex_sbuf_ctl - Represents the registers that set the buffer * parameters for the instruction queues. * * When quiescent (i.e. outstanding doorbell count is 0), it is safe to rewrite * this register to effectively reset the command buffer state machine. * These registers must be programmed before SW programs the corresponding * ZIP_QUE(0..7)_SBUF_ADDR. */ zip_quex_sbuf_ctl; static inline u64 ZIP_QUEX_SBUF_CTL(u64 param1) { … } /** * union zip_que_ena - Represents queue enable register * * If a queue is disabled, ZIP_CTL stops fetching instructions from the queue. */ zip_que_ena; #define ZIP_QUE_ENA … /** * union zip_que_pri - Represents the register that defines the priority * between instruction queues. */ zip_que_pri; #define ZIP_QUE_PRI … /** * union zip_throttle - Represents the register that controls the maximum * number of in-flight X2I data fetch transactions. * * Writing 0 to this register causes the ZIP module to temporarily suspend NCB * accesses; it is not recommended for normal operation, but may be useful for * diagnostics. */ zip_throttle; #define ZIP_THROTTLE … #endif /* _CSRS_ZIP__ */
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