/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ #ifndef __CC_HW_QUEUE_DEFS_H__ #define __CC_HW_QUEUE_DEFS_H__ #include <linux/types.h> #include "cc_kernel_regs.h" #include <linux/bitfield.h> /****************************************************************************** * DEFINITIONS ******************************************************************************/ #define HW_DESC_SIZE_WORDS … /* Define max. available slots in HW queue */ #define HW_QUEUE_SLOTS_MAX … #define CC_REG_LOW(name) … #define CC_REG_HIGH(name) … #define CC_GENMASK(name) … #define CC_HWQ_GENMASK(word, field) … #define WORD0_VALUE … #define WORD0_CPP_CIPHER_MODE … #define WORD1_DIN_CONST_VALUE … #define WORD1_DIN_DMA_MODE … #define WORD1_DIN_SIZE … #define WORD1_NOT_LAST … #define WORD1_NS_BIT … #define WORD1_LOCK_QUEUE … #define WORD2_VALUE … #define WORD3_DOUT_DMA_MODE … #define WORD3_DOUT_LAST_IND … #define WORD3_DOUT_SIZE … #define WORD3_HASH_XOR_BIT … #define WORD3_NS_BIT … #define WORD3_QUEUE_LAST_IND … #define WORD4_ACK_NEEDED … #define WORD4_AES_SEL_N_HASH … #define WORD4_AES_XOR_CRYPTO_KEY … #define WORD4_BYTES_SWAP … #define WORD4_CIPHER_CONF0 … #define WORD4_CIPHER_CONF1 … #define WORD4_CIPHER_CONF2 … #define WORD4_CIPHER_DO … #define WORD4_CIPHER_MODE … #define WORD4_CMAC_SIZE0 … #define WORD4_DATA_FLOW_MODE … #define WORD4_KEY_SIZE … #define WORD4_SETUP_OPERATION … #define WORD5_DIN_ADDR_HIGH … #define WORD5_DOUT_ADDR_HIGH … /****************************************************************************** * TYPE DEFINITIONS ******************************************************************************/ struct cc_hw_desc { … }; enum cc_axi_sec { … }; enum cc_desc_direction { … }; enum cc_dma_mode { … }; enum cc_flow_mode { … }; enum cc_setup_op { … }; enum cc_hash_conf_pad { … }; enum cc_aes_mac_selector { … }; #define HW_KEY_MASK_CIPHER_DO … #define HW_KEY_SHIFT_CIPHER_CFG2 … /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ enum cc_hw_crypto_key { … }; #define CC_NUM_HW_KEY_SLOTS … #define CC_FIRST_HW_KEY_SLOT … #define CC_LAST_HW_KEY_SLOT … #define CC_NUM_CPP_KEY_SLOTS … #define CC_FIRST_CPP_KEY_SLOT … #define CC_LAST_CPP_KEY_SLOT … enum cc_hw_aes_key_size { … }; enum cc_hash_cipher_pad { … }; #define CC_CPP_DIN_ADDR … #define CC_CPP_DIN_SIZE … /*****************************/ /* Descriptor packing macros */ /*****************************/ /** * hw_desc_init() - Init a HW descriptor struct * @pdesc: pointer to HW descriptor struct */ static inline void hw_desc_init(struct cc_hw_desc *pdesc) { … } /** * set_queue_last_ind_bit() - Indicate the end of current HW descriptors flow * and release the HW engines. * * @pdesc: Pointer to HW descriptor struct */ static inline void set_queue_last_ind_bit(struct cc_hw_desc *pdesc) { … } /** * set_din_type() - Set the DIN field of a HW descriptor * * @pdesc: Pointer to HW descriptor struct * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT * @addr: DIN address * @size: Data size in bytes * @axi_sec: AXI secure bit */ static inline void set_din_type(struct cc_hw_desc *pdesc, enum cc_dma_mode dma_mode, dma_addr_t addr, u32 size, enum cc_axi_sec axi_sec) { … } /** * set_din_no_dma() - Set the DIN field of a HW descriptor to NO DMA mode. * Used for NOP descriptor, register patches and other special modes. * * @pdesc: Pointer to HW descriptor struct * @addr: DIN address * @size: Data size in bytes */ static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) { … } /** * set_cpp_crypto_key() - Setup the special CPP descriptor * * @pdesc: Pointer to HW descriptor struct * @slot: Slot number */ static inline void set_cpp_crypto_key(struct cc_hw_desc *pdesc, u8 slot) { … } /** * set_din_sram() - Set the DIN field of a HW descriptor to SRAM mode. * Note: No need to check SRAM alignment since host requests do not use SRAM and * the adaptor will enforce alignment checks. * * @pdesc: Pointer to HW descriptor struct * @addr: DIN address * @size: Data size in bytes */ static inline void set_din_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) { … } /** * set_din_const() - Set the DIN field of a HW descriptor to CONST mode * * @pdesc: Pointer to HW descriptor struct * @val: DIN const value * @size: Data size in bytes */ static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) { … } /** * set_din_not_last_indication() - Set the DIN not last input data indicator * * @pdesc: Pointer to HW descriptor struct */ static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) { … } /** * set_dout_type() - Set the DOUT field of a HW descriptor * * @pdesc: Pointer to HW descriptor struct * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT * @addr: DOUT address * @size: Data size in bytes * @axi_sec: AXI secure bit */ static inline void set_dout_type(struct cc_hw_desc *pdesc, enum cc_dma_mode dma_mode, dma_addr_t addr, u32 size, enum cc_axi_sec axi_sec) { … } /** * set_dout_dlli() - Set the DOUT field of a HW descriptor to DLLI type * The LAST INDICATION is provided by the user * * @pdesc: Pointer to HW descriptor struct * @addr: DOUT address * @size: Data size in bytes * @axi_sec: AXI secure bit * @last_ind: The last indication bit */ static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, u32 size, enum cc_axi_sec axi_sec, u32 last_ind) { … } /** * set_dout_mlli() - Set the DOUT field of a HW descriptor to MLLI type * The LAST INDICATION is provided by the user * * @pdesc: Pointer to HW descriptor struct * @addr: DOUT address * @size: Data size in bytes * @axi_sec: AXI secure bit * @last_ind: The last indication bit */ static inline void set_dout_mlli(struct cc_hw_desc *pdesc, u32 addr, u32 size, enum cc_axi_sec axi_sec, bool last_ind) { … } /** * set_dout_no_dma() - Set the DOUT field of a HW descriptor to NO DMA mode. * Used for NOP descriptor, register patches and other special modes. * * @pdesc: pointer to HW descriptor struct * @addr: DOUT address * @size: Data size in bytes * @write_enable: Enables a write operation to a register */ static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size, bool write_enable) { … } /** * set_xor_val() - Set the word for the XOR operation. * * @pdesc: Pointer to HW descriptor struct * @val: XOR data value */ static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) { … } /** * set_xor_active() - Set the XOR indicator bit in the descriptor * * @pdesc: Pointer to HW descriptor struct */ static inline void set_xor_active(struct cc_hw_desc *pdesc) { … } /** * set_aes_not_hash_mode() - Select the AES engine instead of HASH engine when * setting up combined mode with AES XCBC MAC * * @pdesc: Pointer to HW descriptor struct */ static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) { … } /** * set_aes_xor_crypto_key() - Set aes xor crypto key, which in some scenarios * selects the SM3 engine * * @pdesc: Pointer to HW descriptor struct */ static inline void set_aes_xor_crypto_key(struct cc_hw_desc *pdesc) { … } /** * set_dout_sram() - Set the DOUT field of a HW descriptor to SRAM mode * Note: No need to check SRAM alignment since host requests do not use SRAM and * the adaptor will enforce alignment checks. * * @pdesc: Pointer to HW descriptor struct * @addr: DOUT address * @size: Data size in bytes */ static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) { … } /** * set_xex_data_unit_size() - Set the data unit size for XEX mode in * data_out_addr[15:0] * * @pdesc: Pointer to HW descriptor struct * @size: Data unit size for XEX mode */ static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) { … } /** * set_multi2_num_rounds() - Set the number of rounds for Multi2 in * data_out_addr[15:0] * * @pdesc: Pointer to HW descriptor struct * @num: Number of rounds for Multi2 */ static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) { … } /** * set_flow_mode() - Set the flow mode. * * @pdesc: Pointer to HW descriptor struct * @mode: Any one of the modes defined in [CC7x-DESC] */ static inline void set_flow_mode(struct cc_hw_desc *pdesc, enum cc_flow_mode mode) { … } /** * set_cipher_mode() - Set the cipher mode. * * @pdesc: Pointer to HW descriptor struct * @mode: Any one of the modes defined in [CC7x-DESC] */ static inline void set_cipher_mode(struct cc_hw_desc *pdesc, int mode) { … } /** * set_hash_cipher_mode() - Set the cipher mode for hash algorithms. * * @pdesc: Pointer to HW descriptor struct * @cipher_mode: Any one of the modes defined in [CC7x-DESC] * @hash_mode: specifies which hash is being handled */ static inline void set_hash_cipher_mode(struct cc_hw_desc *pdesc, enum drv_cipher_mode cipher_mode, enum drv_hash_mode hash_mode) { … } /** * set_cipher_config0() - Set the cipher configuration fields. * * @pdesc: Pointer to HW descriptor struct * @mode: Any one of the modes defined in [CC7x-DESC] */ static inline void set_cipher_config0(struct cc_hw_desc *pdesc, int mode) { … } /** * set_cipher_config1() - Set the cipher configuration fields. * * @pdesc: Pointer to HW descriptor struct * @config: Padding mode */ static inline void set_cipher_config1(struct cc_hw_desc *pdesc, enum cc_hash_conf_pad config) { … } /** * set_hw_crypto_key() - Set HW key configuration fields. * * @pdesc: Pointer to HW descriptor struct * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key */ static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, enum cc_hw_crypto_key hw_key) { … } /** * set_bytes_swap() - Set byte order of all setup-finalize descriptors. * * @pdesc: Pointer to HW descriptor struct * @config: True to enable byte swapping */ static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) { … } /** * set_cmac_size0_mode() - Set CMAC_SIZE0 mode. * * @pdesc: Pointer to HW descriptor struct */ static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) { … } /** * set_key_size() - Set key size descriptor field. * * @pdesc: Pointer to HW descriptor struct * @size: Key size in bytes (NOT size code) */ static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) { … } /** * set_key_size_aes() - Set AES key size. * * @pdesc: Pointer to HW descriptor struct * @size: Key size in bytes (NOT size code) */ static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) { … } /** * set_key_size_des() - Set DES key size. * * @pdesc: Pointer to HW descriptor struct * @size: Key size in bytes (NOT size code) */ static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) { … } /** * set_setup_mode() - Set the descriptor setup mode * * @pdesc: Pointer to HW descriptor struct * @mode: Any one of the setup modes defined in [CC7x-DESC] */ static inline void set_setup_mode(struct cc_hw_desc *pdesc, enum cc_setup_op mode) { … } /** * set_cipher_do() - Set the descriptor cipher DO * * @pdesc: Pointer to HW descriptor struct * @config: Any one of the cipher do defined in [CC7x-DESC] */ static inline void set_cipher_do(struct cc_hw_desc *pdesc, enum cc_hash_cipher_pad config) { … } #endif /*__CC_HW_QUEUE_DEFS_H__*/
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