linux/drivers/crypto/ccree/cc_hash.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */

/* \file cc_hash.h
 * ARM CryptoCell Hash Crypto API
 */

#ifndef __CC_HASH_H__
#define __CC_HASH_H__

#include "cc_buffer_mgr.h"

#define HMAC_IPAD_CONST …
#define HMAC_OPAD_CONST …
#define HASH_LEN_SIZE_712 …
#define HASH_LEN_SIZE_630 …
#define HASH_MAX_LEN_SIZE …
#define CC_MAX_HASH_DIGEST_SIZE …
#define CC_MAX_HASH_BLCK_SIZE …

#define XCBC_MAC_K1_OFFSET …
#define XCBC_MAC_K2_OFFSET …
#define XCBC_MAC_K3_OFFSET …

#define CC_EXPORT_MAGIC …

/* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used
 * for xcbc/cmac statesize
 */
struct aeshash_state { … };

/* ahash state */
struct ahash_req_ctx { … };

static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state)
{ … }

static inline u8 *cc_hash_buf(struct ahash_req_ctx *state)
{ … }

static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state)
{ … }

static inline u8 *cc_next_buf(struct ahash_req_ctx *state)
{ … }

int cc_hash_alloc(struct cc_drvdata *drvdata);
int cc_init_hash_sram(struct cc_drvdata *drvdata);
int cc_hash_free(struct cc_drvdata *drvdata);

/**
 * cc_digest_len_addr() - Gets the initial digest length
 *
 * @drvdata: Associated device driver context
 * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
 *
 * Return:
 * Returns the address of the initial digest length in SRAM
 */
u32 cc_digest_len_addr(void *drvdata, u32 mode);

/**
 * cc_larval_digest_addr() - Gets the address of the initial digest in SRAM
 * according to the given hash mode
 *
 * @drvdata: Associated device driver context
 * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
 *
 * Return:
 * The address of the initial digest in SRAM
 */
u32 cc_larval_digest_addr(void *drvdata, u32 mode);

#endif /*__CC_HASH_H__*/