linux/drivers/crypto/ccree/cc_hash.c

// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */

#include <linux/kernel.h>
#include <linux/module.h>
#include <crypto/algapi.h>
#include <crypto/hash.h>
#include <crypto/md5.h>
#include <crypto/sm3.h>
#include <crypto/internal/hash.h>

#include "cc_driver.h"
#include "cc_request_mgr.h"
#include "cc_buffer_mgr.h"
#include "cc_hash.h"
#include "cc_sram_mgr.h"

#define CC_MAX_HASH_SEQ_LEN …
#define CC_MAX_OPAD_KEYS_SIZE …
#define CC_SM3_HASH_LEN_SIZE …

struct cc_hash_handle { … };

static const u32 cc_digest_len_init[] = …;
static const u32 cc_md5_init[] = …;
static const u32 cc_sha1_init[] = …;
static const u32 cc_sha224_init[] = …;
static const u32 cc_sha256_init[] = …;
static const u32 cc_digest_len_sha512_init[] = …;

/*
 * Due to the way the HW works, every double word in the SHA384 and SHA512
 * larval hashes must be stored in hi/lo order
 */
#define hilo(x) …
static const u32 cc_sha384_init[] = …;
static const u32 cc_sha512_init[] = …;

static const u32 cc_sm3_init[] = …;

static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],
			  unsigned int *seq_size);

static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[],
			  unsigned int *seq_size);

static const void *cc_larval_digest(struct device *dev, u32 mode);

struct cc_hash_alg { … };

struct hash_key_req_ctx { … };

/* hash per-session context */
struct cc_hash_ctx { … };

static void cc_set_desc(struct ahash_req_ctx *areq_ctx, struct cc_hash_ctx *ctx,
			unsigned int flow_mode, struct cc_hw_desc desc[],
			bool is_not_last_data, unsigned int *seq_size);

static void cc_set_endianity(u32 mode, struct cc_hw_desc *desc)
{ … }

static int cc_map_result(struct device *dev, struct ahash_req_ctx *state,
			 unsigned int digestsize)
{ … }

static void cc_init_req(struct device *dev, struct ahash_req_ctx *state,
			struct cc_hash_ctx *ctx)
{ … }

static int cc_map_req(struct device *dev, struct ahash_req_ctx *state,
		      struct cc_hash_ctx *ctx)
{ … }

static void cc_unmap_req(struct device *dev, struct ahash_req_ctx *state,
			 struct cc_hash_ctx *ctx)
{ … }

static void cc_unmap_result(struct device *dev, struct ahash_req_ctx *state,
			    unsigned int digestsize, u8 *result)
{ … }

static void cc_update_complete(struct device *dev, void *cc_req, int err)
{ … }

static void cc_digest_complete(struct device *dev, void *cc_req, int err)
{ … }

static void cc_hash_complete(struct device *dev, void *cc_req, int err)
{ … }

static int cc_fin_result(struct cc_hw_desc *desc, struct ahash_request *req,
			 int idx)
{ … }

static int cc_fin_hmac(struct cc_hw_desc *desc, struct ahash_request *req,
		       int idx)
{ … }

static int cc_hash_digest(struct ahash_request *req)
{ … }

static int cc_restore_hash(struct cc_hw_desc *desc, struct cc_hash_ctx *ctx,
			   struct ahash_req_ctx *state, unsigned int idx)
{ … }

static int cc_hash_update(struct ahash_request *req)
{ … }

static int cc_do_finup(struct ahash_request *req, bool update)
{ … }

static int cc_hash_finup(struct ahash_request *req)
{ … }


static int cc_hash_final(struct ahash_request *req)
{ … }

static int cc_hash_init(struct ahash_request *req)
{ … }

static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key,
			  unsigned int keylen)
{ … }

static int cc_xcbc_setkey(struct crypto_ahash *ahash,
			  const u8 *key, unsigned int keylen)
{ … }

static int cc_cmac_setkey(struct crypto_ahash *ahash,
			  const u8 *key, unsigned int keylen)
{ … }

static void cc_free_ctx(struct cc_hash_ctx *ctx)
{ … }

static int cc_alloc_ctx(struct cc_hash_ctx *ctx)
{ … }

static int cc_get_hash_len(struct crypto_tfm *tfm)
{ … }

static int cc_cra_init(struct crypto_tfm *tfm)
{ … }

static void cc_cra_exit(struct crypto_tfm *tfm)
{ … }

static int cc_mac_update(struct ahash_request *req)
{ … }

static int cc_mac_final(struct ahash_request *req)
{ … }

static int cc_mac_finup(struct ahash_request *req)
{ … }

static int cc_mac_digest(struct ahash_request *req)
{ … }

static int cc_hash_export(struct ahash_request *req, void *out)
{ … }

static int cc_hash_import(struct ahash_request *req, const void *in)
{ … }

struct cc_hash_template { … };

#define CC_STATE_SIZE(_x) …

/* hash descriptors */
static struct cc_hash_template driver_hash[] = …;

static struct cc_hash_alg *cc_alloc_hash_alg(struct cc_hash_template *template,
					     struct device *dev, bool keyed)
{ … }

static int cc_init_copy_sram(struct cc_drvdata *drvdata, const u32 *data,
			     unsigned int size, u32 *sram_buff_ofs)
{ … }

int cc_init_hash_sram(struct cc_drvdata *drvdata)
{ … }

int cc_hash_alloc(struct cc_drvdata *drvdata)
{ … }

int cc_hash_free(struct cc_drvdata *drvdata)
{ … }

static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],
			  unsigned int *seq_size)
{ … }

static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[],
			  unsigned int *seq_size)
{ … }

static void cc_set_desc(struct ahash_req_ctx *areq_ctx,
			struct cc_hash_ctx *ctx, unsigned int flow_mode,
			struct cc_hw_desc desc[], bool is_not_last_data,
			unsigned int *seq_size)
{ … }

static const void *cc_larval_digest(struct device *dev, u32 mode)
{ … }

/**
 * cc_larval_digest_addr() - Get the address of the initial digest in SRAM
 * according to the given hash mode
 *
 * @drvdata: Associated device driver context
 * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256
 *
 * Return:
 * The address of the initial digest in SRAM
 */
u32 cc_larval_digest_addr(void *drvdata, u32 mode)
{ … }

u32 cc_digest_len_addr(void *drvdata, u32 mode)
{ … }