/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */ /* \file cc_driver.h * ARM CryptoCell Linux Crypto Driver */ #ifndef __CC_DRIVER_H__ #define __CC_DRIVER_H__ #ifdef COMP_IN_WQ #include <linux/workqueue.h> #else #include <linux/interrupt.h> #endif #include <linux/dma-mapping.h> #include <crypto/algapi.h> #include <crypto/internal/skcipher.h> #include <crypto/aes.h> #include <crypto/sha1.h> #include <crypto/sha2.h> #include <crypto/aead.h> #include <crypto/authenc.h> #include <crypto/hash.h> #include <crypto/skcipher.h> #include <linux/clk.h> #include <linux/platform_device.h> #include "cc_host_regs.h" #include "cc_crypto_ctx.h" #include "cc_hw_queue_defs.h" #include "cc_sram_mgr.h" extern bool cc_dump_desc; extern bool cc_dump_bytes; #define DRV_MODULE_VERSION … enum cc_hw_rev { … }; enum cc_std_body { … }; #define CC_PINS_FULL … #define CC_PINS_SLIM … /* Maximum DMA mask supported by IP */ #define DMA_BIT_MASK_LEN … #define CC_AXI_IRQ_MASK … #define CC_AXI_ERR_IRQ_MASK … #define CC_COMP_IRQ_MASK … #define CC_SECURITY_DISABLED_MASK … #define CC_NVM_IS_IDLE_MASK … #define AXIM_MON_COMP_VALUE … #define CC_CPP_AES_ABORT_MASK … #define CC_CPP_SM4_ABORT_MASK … /* Register name mangling macro */ #define CC_REG(reg_name) … /* TEE FIPS status interrupt */ #define CC_GPR0_IRQ_MASK … #define CC_CRA_PRIO … #define MIN_HW_QUEUE_SIZE … #define MAX_REQUEST_QUEUE_SIZE … #define MAX_MLLI_BUFF_SIZE … /* Definitions for HW descriptors DIN/DOUT fields */ #define NS_BIT … #define AXI_ID … /* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID * field in the HW descriptor. The DMA engine +8 that value. */ struct cc_cpp_req { … }; #define CC_MAX_IVGEN_DMA_ADDRESSES … struct cc_crypto_req { … }; /** * struct cc_drvdata - driver private data context * @cc_base: virt address of the CC registers * @irq: bitmap indicating source of last interrupt */ struct cc_drvdata { … }; struct cc_crypto_alg { … }; struct cc_alg_template { … }; struct async_gen_req_ctx { … }; static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata) { … } void __dump_byte_array(const char *name, const u8 *buf, size_t len); static inline void dump_byte_array(const char *name, const u8 *the_array, size_t size) { … } bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata); int init_cc_regs(struct cc_drvdata *drvdata); void fini_cc_regs(struct cc_drvdata *drvdata); unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata); static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val) { … } static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg) { … } static inline gfp_t cc_gfp_flags(struct crypto_async_request *req) { … } static inline void set_queue_last_ind(struct cc_drvdata *drvdata, struct cc_hw_desc *pdesc) { … } #endif /*__CC_DRIVER_H__*/
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