/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __NITROX_DEV_H #define __NITROX_DEV_H #include <linux/dma-mapping.h> #include <linux/interrupt.h> #include <linux/pci.h> #include <linux/if.h> #define VERSION_LEN … /* Maximum queues in PF mode */ #define MAX_PF_QUEUES … /* Maximum device queues */ #define MAX_DEV_QUEUES … /* Maximum UCD Blocks */ #define CNN55XX_MAX_UCD_BLOCKS … /** * struct nitrox_cmdq - NITROX command queue * @cmd_qlock: command queue lock * @resp_qlock: response queue lock * @backlog_qlock: backlog queue lock * @ndev: NITROX device * @response_head: submitted request list * @backlog_head: backlog queue * @dbell_csr_addr: doorbell register address for this queue * @compl_cnt_csr_addr: completion count register address of the slc port * @base: command queue base address * @dma: dma address of the base * @pending_count: request pending at device * @backlog_count: backlog request count * @write_idx: next write index for the command * @instr_size: command size * @qno: command queue number * @qsize: command queue size * @unalign_base: unaligned base address * @unalign_dma: unaligned dma address */ struct nitrox_cmdq { … }; /** * struct nitrox_hw - NITROX hardware information * @partname: partname ex: CNN55xxx-xxx * @fw_name: firmware version * @freq: NITROX frequency * @vendor_id: vendor ID * @device_id: device ID * @revision_id: revision ID * @se_cores: number of symmetric cores * @ae_cores: number of asymmetric cores * @zip_cores: number of zip cores */ struct nitrox_hw { … }; struct nitrox_stats { … }; #define IRQ_NAMESZ … struct nitrox_q_vector { … }; enum mcode_type { … }; /** * mbox_msg - Mailbox message data * @type: message type * @opcode: message opcode * @data: message data */ mbox_msg; /** * nitrox_vfdev - NITROX VF device instance in PF * @state: VF device state * @vfno: VF number * @nr_queues: number of queues enabled in VF * @ring: ring to communicate with VF * @msg: Mailbox message data from VF * @mbx_resp: Mailbox counters */ struct nitrox_vfdev { … }; /** * struct nitrox_iov - SR-IOV information * @num_vfs: number of VF(s) enabled * @max_vf_queues: Maximum number of queues allowed for VF * @vfdev: VF(s) devices * @pf2vf_wq: workqueue for PF2VF communication * @msix: MSI-X entry for PF in SR-IOV case */ struct nitrox_iov { … }; /* * NITROX Device states */ enum ndev_state { … }; /* NITROX support modes for VF(s) */ enum vf_mode { … }; #define __NDEV_SRIOV_BIT … /* command queue size */ #define DEFAULT_CMD_QLEN … /* command timeout in milliseconds */ #define CMD_TIMEOUT … #define DEV(ndev) … #define NITROX_CSR_ADDR(ndev, offset) … /** * struct nitrox_device - NITROX Device Information. * @list: pointer to linked list of devices * @bar_addr: iomap address * @pdev: PCI device information * @state: NITROX device state * @flags: flags to indicate device the features * @timeout: Request timeout in jiffies * @refcnt: Device usage count * @idx: device index (0..N) * @node: NUMA node id attached * @qlen: Command queue length * @nr_queues: Number of command queues * @mode: Device mode PF/VF * @ctx_pool: DMA pool for crypto context * @pkt_inq: Packet input rings * @aqmq: AQM command queues * @qvec: MSI-X queue vectors information * @iov: SR-IOV informatin * @num_vecs: number of MSI-X vectors * @stats: request statistics * @hw: hardware information * @debugfs_dir: debugfs directory */ struct nitrox_device { … }; /** * nitrox_read_csr - Read from device register * @ndev: NITROX device * @offset: offset of the register to read * * Returns: value read */ static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) { … } /** * nitrox_write_csr - Write to device register * @ndev: NITROX device * @offset: offset of the register to write * @value: value to write */ static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, u64 value) { … } static inline bool nitrox_ready(struct nitrox_device *ndev) { … } static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev) { … } #endif /* __NITROX_DEV_H */
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