/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __NITROX_CSR_H #define __NITROX_CSR_H #include <asm/byteorder.h> #include <linux/types.h> /* EMU clusters */ #define NR_CLUSTERS … /* Maximum cores per cluster, * varies based on partname */ #define AE_CORES_PER_CLUSTER … #define SE_CORES_PER_CLUSTER … #define AE_MAX_CORES … #define SE_MAX_CORES … #define ZIP_MAX_CORES … /* BIST registers */ #define EMU_BIST_STATUSX(_i) … #define UCD_BIST_STATUS … #define NPS_CORE_BIST_REG … #define NPS_CORE_NPC_BIST_REG … #define NPS_PKT_SLC_BIST_REG … #define NPS_PKT_IN_BIST_REG … #define POM_BIST_REG … #define BMI_BIST_REG … #define EFL_CORE_BIST_REGX(_i) … #define EFL_TOP_BIST_STAT … #define BMO_BIST_REG … #define LBC_BIST_STATUS … #define PEM_BIST_STATUSX(_i) … /* EMU registers */ #define EMU_SE_ENABLEX(_i) … #define EMU_AE_ENABLEX(_i) … #define EMU_WD_INT_ENA_W1SX(_i) … #define EMU_GE_INT_ENA_W1SX(_i) … #define EMU_FUSE_MAPX(_i) … /* UCD registers */ #define UCD_SE_EID_UCODE_BLOCK_NUMX(_i) … #define UCD_AE_EID_UCODE_BLOCK_NUMX(_i) … #define UCD_UCODE_LOAD_BLOCK_NUM … #define UCD_UCODE_LOAD_IDX_DATAX(_i) … #define UCD_SE_CNTX(_i) … #define UCD_AE_CNTX(_i) … /* AQM registers */ #define AQM_CTL … #define AQM_INT … #define AQM_DBELL_OVF_LO … #define AQM_DBELL_OVF_HI … #define AQM_DBELL_OVF_LO_W1S … #define AQM_DBELL_OVF_LO_ENA_W1C … #define AQM_DBELL_OVF_LO_ENA_W1S … #define AQM_DBELL_OVF_HI_W1S … #define AQM_DBELL_OVF_HI_ENA_W1C … #define AQM_DBELL_OVF_HI_ENA_W1S … #define AQM_DMA_RD_ERR_LO … #define AQM_DMA_RD_ERR_HI … #define AQM_DMA_RD_ERR_LO_W1S … #define AQM_DMA_RD_ERR_LO_ENA_W1C … #define AQM_DMA_RD_ERR_LO_ENA_W1S … #define AQM_DMA_RD_ERR_HI_W1S … #define AQM_DMA_RD_ERR_HI_ENA_W1C … #define AQM_DMA_RD_ERR_HI_ENA_W1S … #define AQM_EXEC_NA_LO … #define AQM_EXEC_NA_HI … #define AQM_EXEC_NA_LO_W1S … #define AQM_EXEC_NA_LO_ENA_W1C … #define AQM_EXEC_NA_LO_ENA_W1S … #define AQM_EXEC_NA_HI_W1S … #define AQM_EXEC_NA_HI_ENA_W1C … #define AQM_EXEC_NA_HI_ENA_W1S … #define AQM_EXEC_ERR_LO … #define AQM_EXEC_ERR_HI … #define AQM_EXEC_ERR_LO_W1S … #define AQM_EXEC_ERR_LO_ENA_W1C … #define AQM_EXEC_ERR_LO_ENA_W1S … #define AQM_EXEC_ERR_HI_W1S … #define AQM_EXEC_ERR_HI_ENA_W1C … #define AQM_EXEC_ERR_HI_ENA_W1S … #define AQM_ECC_INT … #define AQM_ECC_INT_W1S … #define AQM_ECC_INT_ENA_W1C … #define AQM_ECC_INT_ENA_W1S … #define AQM_ECC_CTL … #define AQM_BIST_STATUS … #define AQM_CMD_INF_THRX(x) … #define AQM_CMD_INFX(x) … #define AQM_GRP_EXECMSK_LOX(x) … #define AQM_GRP_EXECMSK_HIX(x) … #define AQM_ACTIVITY_STAT_LO … #define AQM_ACTIVITY_STAT_HI … #define AQM_Q_CMD_PROCX(x) … #define AQM_PERF_CTL_LO … #define AQM_PERF_CTL_HI … #define AQM_PERF_CNT … #define AQMQ_DRBLX(x) … #define AQMQ_QSZX(x) … #define AQMQ_BADRX(x) … #define AQMQ_NXT_CMDX(x) … #define AQMQ_CMD_CNTX(x) … #define AQMQ_CMP_THRX(x) … #define AQMQ_CMP_CNTX(x) … #define AQMQ_TIM_LDX(x) … #define AQMQ_TIMERX(x) … #define AQMQ_ENX(x) … #define AQMQ_ACTIVITY_STATX(x) … #define AQM_VF_CMP_STATX(x) … /* NPS core registers */ #define NPS_CORE_GBL_VFCFG … #define NPS_CORE_CONTROL … #define NPS_CORE_INT_ACTIVE … #define NPS_CORE_INT … #define NPS_CORE_INT_ENA_W1S … #define NPS_STATS_PKT_DMA_RD_CNT … #define NPS_STATS_PKT_DMA_WR_CNT … /* NPS packet registers */ #define NPS_PKT_INT … #define NPS_PKT_MBOX_INT_LO … #define NPS_PKT_MBOX_INT_LO_ENA_W1C … #define NPS_PKT_MBOX_INT_LO_ENA_W1S … #define NPS_PKT_MBOX_INT_HI … #define NPS_PKT_MBOX_INT_HI_ENA_W1C … #define NPS_PKT_MBOX_INT_HI_ENA_W1S … #define NPS_PKT_IN_RERR_HI … #define NPS_PKT_IN_RERR_HI_ENA_W1S … #define NPS_PKT_IN_RERR_LO … #define NPS_PKT_IN_RERR_LO_ENA_W1S … #define NPS_PKT_IN_ERR_TYPE … #define NPS_PKT_IN_ERR_TYPE_ENA_W1S … #define NPS_PKT_IN_INSTR_CTLX(_i) … #define NPS_PKT_IN_INSTR_BADDRX(_i) … #define NPS_PKT_IN_INSTR_RSIZEX(_i) … #define NPS_PKT_IN_DONE_CNTSX(_i) … #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) … #define NPS_PKT_IN_INT_LEVELSX(_i) … #define NPS_PKT_SLC_RERR_HI … #define NPS_PKT_SLC_RERR_HI_ENA_W1S … #define NPS_PKT_SLC_RERR_LO … #define NPS_PKT_SLC_RERR_LO_ENA_W1S … #define NPS_PKT_SLC_ERR_TYPE … #define NPS_PKT_SLC_ERR_TYPE_ENA_W1S … /* Mailbox PF->VF PF Accessible Data registers */ #define NPS_PKT_MBOX_PF_VF_PFDATAX(_i) … #define NPS_PKT_MBOX_VF_PF_PFDATAX(_i) … #define NPS_PKT_SLC_CTLX(_i) … #define NPS_PKT_SLC_CNTSX(_i) … #define NPS_PKT_SLC_INT_LEVELSX(_i) … /* POM registers */ #define POM_INT_ENA_W1S … #define POM_GRP_EXECMASKX(_i) … #define POM_INT … #define POM_PERF_CTL … /* BMI registers */ #define BMI_INT … #define BMI_CTL … #define BMI_INT_ENA_W1S … #define BMI_NPS_PKT_CNT … /* EFL registers */ #define EFL_CORE_INT_ENA_W1SX(_i) … #define EFL_CORE_VF_ERR_INT0X(_i) … #define EFL_CORE_VF_ERR_INT0_ENA_W1SX(_i) … #define EFL_CORE_VF_ERR_INT1X(_i) … #define EFL_CORE_VF_ERR_INT1_ENA_W1SX(_i) … #define EFL_CORE_SE_ERR_INTX(_i) … #define EFL_RNM_CTL_STATUS … #define EFL_CORE_INTX(_i) … /* BMO registers */ #define BMO_CTL2 … #define BMO_NPS_SLC_PKT_CNT … /* LBC registers */ #define LBC_INT … #define LBC_INVAL_CTL … #define LBC_PLM_VF1_64_INT … #define LBC_INVAL_STATUS … #define LBC_INT_ENA_W1S … #define LBC_PLM_VF1_64_INT_ENA_W1S … #define LBC_PLM_VF65_128_INT … #define LBC_ELM_VF1_64_INT … #define LBC_PLM_VF65_128_INT_ENA_W1S … #define LBC_ELM_VF1_64_INT_ENA_W1S … #define LBC_ELM_VF65_128_INT … #define LBC_ELM_VF65_128_INT_ENA_W1S … #define RST_BOOT … #define FUS_DAT1 … /* PEM registers */ #define PEM0_INT … /** * struct ucd_core_eid_ucode_block_num - Core Eid to Ucode Blk Mapping Registers * @ucode_len: Ucode length identifier 32KB or 64KB * @ucode_blk: Ucode Block Number */ ucd_core_eid_ucode_block_num; /** * struct aqm_grp_execmsk_lo - Available AE engines for the group * @exec_0_to_39: AE engines 0 to 39 status */ aqm_grp_execmsk_lo; /** * struct aqm_grp_execmsk_hi - Available AE engines for the group * @exec_40_to_79: AE engines 40 to 79 status */ aqm_grp_execmsk_hi; /** * struct aqmq_drbl - AQM Queue Doorbell Counter Registers * @dbell_count: Doorbell Counter */ aqmq_drbl; /** * struct aqmq_qsz - AQM Queue Host Queue Size Registers * @host_queue_size: Size, in numbers of 'aqmq_command_s' command * of the Host Ring. */ aqmq_qsz; /** * struct aqmq_cmp_thr - AQM Queue Commands Completed Threshold Registers * @commands_completed_threshold: Count of 'aqmq_command_s' commands executed * by AE engines for which completion interrupt is asserted. */ aqmq_cmp_thr; /** * struct aqmq_cmp_cnt - AQM Queue Commands Completed Count Registers * @resend: Bit to request completion interrupt Resend. * @completion_status: Command completion status of the ring. * @commands_completed_count: Count of 'aqmq_command_s' commands executed by * AE engines. */ aqmq_cmp_cnt; /** * struct aqmq_en - AQM Queue Enable Registers * @queue_status: 1 = AQMQ is enabled, 0 = AQMQ is disabled */ aqmq_en; /** * struct aqmq_activity_stat - AQM Queue Activity Status Registers * @queue_active: 1 = AQMQ is active, 0 = AQMQ is quiescent */ aqmq_activity_stat; /** * struct emu_fuse_map - EMU Fuse Map Registers * @ae_fuse: Fuse settings for AE 19..0 * @se_fuse: Fuse settings for SE 15..0 * * A set bit indicates the unit is fuse disabled. */ emu_fuse_map; /** * struct emu_se_enable - Symmetric Engine Enable Registers * @enable: Individual enables for each of the clusters * 16 symmetric engines. */ emu_se_enable; /** * struct emu_ae_enable - EMU Asymmetric engines. * @enable: Individual enables for each of the cluster's * 20 Asymmetric Engines. */ emu_ae_enable; /** * struct emu_wd_int_ena_w1s - EMU Interrupt Enable Registers * @ae_wd: Reads or sets enable for EMU(0..3)_WD_INT[AE_WD] * @se_wd: Reads or sets enable for EMU(0..3)_WD_INT[SE_WD] */ emu_wd_int_ena_w1s; /** * struct emu_ge_int_ena_w1s - EMU Interrupt Enable set registers * @ae_ge: Reads or sets enable for EMU(0..3)_GE_INT[AE_GE] * @se_ge: Reads or sets enable for EMU(0..3)_GE_INT[SE_GE] */ emu_ge_int_ena_w1s; /** * struct nps_pkt_slc_ctl - Solicited Packet Out Control Registers * @rh: Indicates whether to remove or include the response header * 1 = Include, 0 = Remove * @z: If set, 8 trailing 0x00 bytes will be added to the end of the * outgoing packet. * @enb: Enable for this port. */ nps_pkt_slc_ctl; /** * struct nps_pkt_slc_cnts - Solicited Packet Out Count Registers * @slc_int: Returns a 1 when: * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET]. * To clear the bit, the CNTS register must be written to clear. * @in_int: Returns a 1 when: * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT]. * To clear the bit, the DONE_CNTS register must be written to clear. * @mbox_int: Returns a 1 when: * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. To clear the bit, * write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] with 1. * @timer: Timer, incremented every 2048 coprocessor clock cycles * when [CNT] is not zero. The hardware clears both [TIMER] and * [INT] when [CNT] goes to 0. * @cnt: Packet counter. Hardware adds to [CNT] as it sends packets out. * On a write to this CSR, hardware subtracts the amount written to the * [CNT] field from [CNT]. */ nps_pkt_slc_cnts; /** * struct nps_pkt_slc_int_levels - Solicited Packet Out Interrupt Levels * Registers. * @bmode: Determines whether NPS_PKT_SLC_CNTS[CNT] is a byte or * packet counter. * @timet: Output port counter time interrupt threshold. * @cnt: Output port counter interrupt threshold. */ nps_pkt_slc_int_levels; /** * struct nps_pkt_inst - NPS Packet Interrupt Register * @in_err: Set when any NPS_PKT_IN_RERR_HI/LO bit and * corresponding NPS_PKT_IN_RERR_*_ENA_* bit are bot set. * @uns_err: Set when any NSP_PKT_UNS_RERR_HI/LO bit and * corresponding NPS_PKT_UNS_RERR_*_ENA_* bit are both set. * @slc_er: Set when any NSP_PKT_SLC_RERR_HI/LO bit and * corresponding NPS_PKT_SLC_RERR_*_ENA_* bit are both set. */ nps_pkt_int; /** * struct nps_pkt_in_done_cnts - Input instruction ring counts registers * @slc_cnt: Returns a 1 when: * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT], or * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SCL(i)_INT_LEVELS[TIMET] * To clear the bit, the CNTS register must be * written to clear the underlying condition * @uns_int: Return a 1 when: * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT], or * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET] * To clear the bit, the CNTS register must be * written to clear the underlying condition * @in_int: Returns a 1 when: * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT] * To clear the bit, the DONE_CNTS register * must be written to clear the underlying condition * @mbox_int: Returns a 1 when: * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set. * To clear the bit, write NPS_PKT_MBOX_PF_VF(i)_INT[INTR] * with 1. * @resend: A write of 1 will resend an MSI-X interrupt message if any * of the following conditions are true for this ring "i". * NPS_PKT_SLC(i)_CNTS[CNT] > NPS_PKT_SLC(i)_INT_LEVELS[CNT] * NPS_PKT_SLC(i)_CNTS[TIMER] > NPS_PKT_SLC(i)_INT_LEVELS[TIMET] * NPS_PKT_UNS(i)_CNTS[CNT] > NPS_PKT_UNS(i)_INT_LEVELS[CNT] * NPS_PKT_UNS(i)_CNTS[TIMER] > NPS_PKT_UNS(i)_INT_LEVELS[TIMET] * NPS_PKT_IN(i)_DONE_CNTS[CNT] > NPS_PKT_IN(i)_INT_LEVELS[CNT] * NPS_PKT_MBOX_PF_VF(i)_INT[INTR] is set * @cnt: Packet counter. Hardware adds to [CNT] as it reads * packets. On a write to this CSR, hardware substracts the * amount written to the [CNT] field from [CNT], which will * clear PKT_IN(i)_INT_STATUS[INTR] if [CNT] becomes <= * NPS_PKT_IN(i)_INT_LEVELS[CNT]. This register should be * cleared before enabling a ring by reading the current * value and writing it back. */ nps_pkt_in_done_cnts; /** * struct nps_pkt_in_instr_ctl - Input Instruction Ring Control Registers. * @is64b: If 1, the ring uses 64-byte instructions. If 0, the * ring uses 32-byte instructions. * @enb: Enable for the input ring. */ nps_pkt_in_instr_ctl; /** * struct nps_pkt_in_instr_rsize - Input instruction ring size registers * @rsize: Ring size (number of instructions) */ nps_pkt_in_instr_rsize; /** * struct nps_pkt_in_instr_baoff_dbell - Input instruction ring * base address offset and doorbell registers * @aoff: Address offset. The offset from the NPS_PKT_IN_INSTR_BADDR * where the next pointer is read. * @dbell: Pointer list doorbell count. Write operations to this field * increments the present value here. Read operations return the * present value. */ nps_pkt_in_instr_baoff_dbell; /** * struct nps_core_int_ena_w1s - NPS core interrupt enable set register * @host_nps_wr_err: Reads or sets enable for * NPS_CORE_INT[HOST_NPS_WR_ERR]. * @npco_dma_malform: Reads or sets enable for * NPS_CORE_INT[NPCO_DMA_MALFORM]. * @exec_wr_timeout: Reads or sets enable for * NPS_CORE_INT[EXEC_WR_TIMEOUT]. * @host_wr_timeout: Reads or sets enable for * NPS_CORE_INT[HOST_WR_TIMEOUT]. * @host_wr_err: Reads or sets enable for * NPS_CORE_INT[HOST_WR_ERR] */ nps_core_int_ena_w1s; /** * struct nps_core_gbl_vfcfg - Global VF Configuration Register. * @ilk_disable: When set, this bit indicates that the ILK interface has * been disabled. * @obaf: BMO allocation control * 0 = allocate per queue * 1 = allocate per VF * @ibaf: BMI allocation control * 0 = allocate per queue * 1 = allocate per VF * @zaf: ZIP allocation control * 0 = allocate per queue * 1 = allocate per VF * @aeaf: AE allocation control * 0 = allocate per queue * 1 = allocate per VF * @seaf: SE allocation control * 0 = allocation per queue * 1 = allocate per VF * @cfg: VF/PF mode. */ nps_core_gbl_vfcfg; /** * struct nps_core_int_active - NPS Core Interrupt Active Register * @resend: Resend MSI-X interrupt if needs to handle interrupts * Sofware can set this bit and then exit the ISR. * @ocla: Set when any OCLA(0)_INT and corresponding OCLA(0_INT_ENA_W1C * bit are set * @mbox: Set when any NPS_PKT_MBOX_INT_LO/HI and corresponding * NPS_PKT_MBOX_INT_LO_ENA_W1C/HI_ENA_W1C bits are set * @emu: bit i is set in [EMU] when any EMU(i)_INT bit is set * @bmo: Set when any BMO_INT bit is set * @bmi: Set when any BMI_INT bit is set or when any non-RO * BMI_INT and corresponding BMI_INT_ENA_W1C bits are both set * @aqm: Set when any AQM_INT bit is set * @zqm: Set when any ZQM_INT bit is set * @efl: Set when any EFL_INT RO bit is set or when any non-RO EFL_INT * and corresponding EFL_INT_ENA_W1C bits are both set * @ilk: Set when any ILK_INT bit is set * @lbc: Set when any LBC_INT RO bit is set or when any non-RO LBC_INT * and corresponding LBC_INT_ENA_W1C bits are bot set * @pem: Set when any PEM(0)_INT RO bit is set or when any non-RO * PEM(0)_INT and corresponding PEM(0)_INT_ENA_W1C bit are both set * @ucd: Set when any UCD_INT bit is set * @zctl: Set when any ZIP_INT RO bit is set or when any non-RO ZIP_INT * and corresponding ZIP_INT_ENA_W1C bits are both set * @lbm: Set when any LBM_INT bit is set * @nps_pkt: Set when any NPS_PKT_INT bit is set * @nps_core: Set when any NPS_CORE_INT RO bit is set or when non-RO * NPS_CORE_INT and corresponding NSP_CORE_INT_ENA_W1C bits are both set */ nps_core_int_active; /** * struct efl_core_int - EFL Interrupt Registers * @epci_decode_err: EPCI decoded a transacation that was unknown * This error should only occurred when there is a micrcode/SE error * and should be considered fatal * @ae_err: An AE uncorrectable error occurred. * See EFL_CORE(0..3)_AE_ERR_INT * @se_err: An SE uncorrectable error occurred. * See EFL_CORE(0..3)_SE_ERR_INT * @dbe: Double-bit error occurred in EFL * @sbe: Single-bit error occurred in EFL * @d_left: Asserted when new POM-Header-BMI-data is * being sent to an Exec, and that Exec has Not read all BMI * data associated with the previous POM header * @len_ovr: Asserted when an Exec-Read is issued that is more than * 14 greater in length that the BMI data left to be read */ efl_core_int; /** * struct efl_core_int_ena_w1s - EFL core interrupt enable set register * @epci_decode_err: Reads or sets enable for * EFL_CORE(0..3)_INT[EPCI_DECODE_ERR]. * @d_left: Reads or sets enable for * EFL_CORE(0..3)_INT[D_LEFT]. * @len_ovr: Reads or sets enable for * EFL_CORE(0..3)_INT[LEN_OVR]. */ efl_core_int_ena_w1s; /** * struct efl_rnm_ctl_status - RNM Control and Status Register * @ent_sel: Select input to RNM FIFO * @exp_ent: Exported entropy enable for random number generator * @rng_rst: Reset to RNG. Setting this bit to 1 cancels the generation * of the current random number. * @rnm_rst: Reset the RNM. Setting this bit to 1 clears all sorted numbers * in the random number memory. * @rng_en: Enabled the output of the RNG. * @ent_en: Entropy enable for random number generator. */ efl_rnm_ctl_status; /** * struct bmi_ctl - BMI control register * @ilk_hdrq_thrsh: Maximum number of header queue locations * that ILK packets may consume. When the threshold is * exceeded ILK_XOFF is sent to the BMI_X2P_ARB. * @nps_hdrq_thrsh: Maximum number of header queue locations * that NPS packets may consume. When the threshold is * exceeded NPS_XOFF is sent to the BMI_X2P_ARB. * @totl_hdrq_thrsh: Maximum number of header queue locations * that the sum of ILK and NPS packets may consume. * @ilk_free_thrsh: Maximum number of buffers that ILK packet * flows may consume before ILK_XOFF is sent to the BMI_X2P_ARB. * @nps_free_thrsh: Maximum number of buffers that NPS packet * flows may consume before NPS XOFF is sent to the BMI_X2p_ARB. * @totl_free_thrsh: Maximum number of buffers that bot ILK and NPS * packet flows may consume before both NPS_XOFF and ILK_XOFF * are asserted to the BMI_X2P_ARB. * @max_pkt_len: Maximum packet length, integral number of 256B * buffers. */ bmi_ctl; /** * struct bmi_int_ena_w1s - BMI interrupt enable set register * @ilk_req_oflw: Reads or sets enable for * BMI_INT[ILK_REQ_OFLW]. * @nps_req_oflw: Reads or sets enable for * BMI_INT[NPS_REQ_OFLW]. * @fpf_undrrn: Reads or sets enable for * BMI_INT[FPF_UNDRRN]. * @eop_err_ilk: Reads or sets enable for * BMI_INT[EOP_ERR_ILK]. * @eop_err_nps: Reads or sets enable for * BMI_INT[EOP_ERR_NPS]. * @sop_err_ilk: Reads or sets enable for * BMI_INT[SOP_ERR_ILK]. * @sop_err_nps: Reads or sets enable for * BMI_INT[SOP_ERR_NPS]. * @pkt_rcv_err_ilk: Reads or sets enable for * BMI_INT[PKT_RCV_ERR_ILK]. * @pkt_rcv_err_nps: Reads or sets enable for * BMI_INT[PKT_RCV_ERR_NPS]. * @max_len_err_ilk: Reads or sets enable for * BMI_INT[MAX_LEN_ERR_ILK]. * @max_len_err_nps: Reads or sets enable for * BMI_INT[MAX_LEN_ERR_NPS]. */ bmi_int_ena_w1s; /** * struct bmo_ctl2 - BMO Control2 Register * @arb_sel: Determines P2X Arbitration * @ilk_buf_thrsh: Maximum number of buffers that the * ILK packet flows may consume before ILK XOFF is * asserted to the POM. * @nps_slc_buf_thrsh: Maximum number of buffers that the * NPS_SLC packet flow may consume before NPS_SLC XOFF is * asserted to the POM. * @nps_uns_buf_thrsh: Maximum number of buffers that the * NPS_UNS packet flow may consume before NPS_UNS XOFF is * asserted to the POM. * @totl_buf_thrsh: Maximum number of buffers that ILK, NPS_UNS and * NPS_SLC packet flows may consume before NPS_UNS XOFF, NSP_SLC and * ILK_XOFF are all asserted POM. */ bmo_ctl2; /** * struct pom_int_ena_w1s - POM interrupt enable set register * @illegal_intf: Reads or sets enable for POM_INT[ILLEGAL_INTF]. * @illegal_dport: Reads or sets enable for POM_INT[ILLEGAL_DPORT]. */ pom_int_ena_w1s; /** * struct lbc_inval_ctl - LBC invalidation control register * @wait_timer: Wait timer for wait state. [WAIT_TIMER] must * always be written with its reset value. * @cam_inval_start: Software should write [CAM_INVAL_START]=1 * to initiate an LBC cache invalidation. After this, software * should read LBC_INVAL_STATUS until LBC_INVAL_STATUS[DONE] is set. * LBC hardware clears [CAVM_INVAL_START] before software can * observed LBC_INVAL_STATUS[DONE] to be set */ lbc_inval_ctl; /** * struct lbc_int_ena_w1s - LBC interrupt enable set register * @cam_hard_err: Reads or sets enable for LBC_INT[CAM_HARD_ERR]. * @cam_inval_abort: Reads or sets enable for LBC_INT[CAM_INVAL_ABORT]. * @over_fetch_err: Reads or sets enable for LBC_INT[OVER_FETCH_ERR]. * @cache_line_to_err: Reads or sets enable for * LBC_INT[CACHE_LINE_TO_ERR]. * @cam_soft_err: Reads or sets enable for * LBC_INT[CAM_SOFT_ERR]. * @dma_rd_err: Reads or sets enable for * LBC_INT[DMA_RD_ERR]. */ lbc_int_ena_w1s; /** * struct lbc_int - LBC interrupt summary register * @cam_hard_err: indicates a fatal hardware error. * It requires system reset. * When [CAM_HARD_ERR] is set, LBC stops logging any new information in * LBC_POM_MISS_INFO_LOG, * LBC_POM_MISS_ADDR_LOG, * LBC_EFL_MISS_INFO_LOG, and * LBC_EFL_MISS_ADDR_LOG. * Software should sample them. * @cam_inval_abort: indicates a fatal hardware error. * System reset is required. * @over_fetch_err: indicates a fatal hardware error * System reset is required * @cache_line_to_err: is a debug feature. * This timeout interrupt bit tells the software that * a cacheline in LBC has non-zero usage and the context * has not been used for greater than the * LBC_TO_CNT[TO_CNT] time interval. * @sbe: Memory SBE error. This is recoverable via ECC. * See LBC_ECC_INT for more details. * @dbe: Memory DBE error. This is a fatal and requires a * system reset. * @pref_dat_len_mismatch_err: Summary bit for context length * mismatch errors. * @rd_dat_len_mismatch_err: Summary bit for SE read data length * greater than data prefect length errors. * @cam_soft_err: is recoverable. Software must complete a * LBC_INVAL_CTL[CAM_INVAL_START] invalidation sequence and * then clear [CAM_SOFT_ERR]. * @dma_rd_err: A context prefect read of host memory returned with * a read error. */ lbc_int; /** * struct lbc_inval_status: LBC Invalidation status register * @cam_clean_entry_complete_cnt: The number of entries that are * cleaned up successfully. * @cam_clean_entry_cnt: The number of entries that have the CAM * inval command issued. * @cam_inval_state: cam invalidation FSM state * @cam_inval_abort: cam invalidation abort * @cam_rst_rdy: lbc_cam reset ready * @done: LBC clears [DONE] when * LBC_INVAL_CTL[CAM_INVAL_START] is written with a one, * and sets [DONE] when it completes the invalidation * sequence. */ lbc_inval_status; /** * struct rst_boot: RST Boot Register * @jtcsrdis: when set, internal CSR access via JTAG TAP controller * is disabled * @jt_tst_mode: JTAG test mode * @io_supply: I/O power supply setting based on IO_VDD_SELECT pin: * 0x1 = 1.8V * 0x2 = 2.5V * 0x4 = 3.3V * All other values are reserved * @pnr_mul: clock multiplier * @lboot: last boot cause mask, resets only with PLL_DC_OK * @rboot: determines whether core 0 remains in reset after * chip cold or warm or soft reset * @rboot_pin: read only access to REMOTE_BOOT pin */ rst_boot; /** * struct fus_dat1: Fuse Data 1 Register * @pll_mul: main clock PLL multiplier hardware limit * @pll_half_dis: main clock PLL control * @efus_lck: efuse lockdown * @zip_info: ZIP information * @bar2_sz_conf: when zero, BAR2 size conforms to * PCIe specification * @efus_ign: efuse ignore * @nozip: ZIP disable * @pll_alt_matrix: select alternate PLL matrix * @pll_bwadj_denom: select CLKF denominator for * BWADJ value * @chip_id: chip ID */ fus_dat1; #endif /* __NITROX_CSR_H */
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