/* SPDX-License-Identifier: GPL-2.0 */ /* * CAAM hardware register-level view * * Copyright 2008-2011 Freescale Semiconductor, Inc. * Copyright 2018, 2023 NXP */ #ifndef REGS_H #define REGS_H #include <linux/types.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/io-64-nonatomic-hi-lo.h> /* * Architecture-specific register access methods * * CAAM's bus-addressable registers are 64 bits internally. * They have been wired to be safely accessible on 32-bit * architectures, however. Registers were organized such * that (a) they can be contained in 32 bits, (b) if not, then they * can be treated as two 32-bit entities, or finally (c) if they * must be treated as a single 64-bit value, then this can safely * be done with two 32-bit cycles. * * For 32-bit operations on 64-bit values, CAAM follows the same * 64-bit register access conventions as it's predecessors, in that * writes are "triggered" by a write to the register at the numerically * higher address, thus, a full 64-bit write cycle requires a write * to the lower address, followed by a write to the higher address, * which will latch/execute the write cycle. * * For example, let's assume a SW reset of CAAM through the master * configuration register. * - SWRST is in bit 31 of MCFG. * - MCFG begins at base+0x0000. * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) * * (and on Power, the convention is 0-31, 32-63, I know...) * * Assuming a 64-bit write to this MCFG to perform a software reset * would then require a write of 0 to base+0x0000, followed by a * write of 0x80000000 to base+0x0004, which would "execute" the * reset. * * Of course, since MCFG 63-32 is all zero, we could cheat and simply * write 0x8000000 to base+0x0004, and the reset would work fine. * However, since CAAM does contain some write-and-read-intended * 64-bit registers, this code defines 64-bit access methods for * the sake of internal consistency and simplicity, and so that a * clean transition to 64-bit is possible when it becomes necessary. * * There are limitations to this that the developer must recognize. * 32-bit architectures cannot enforce an atomic-64 operation, * Therefore: * * - On writes, since the HW is assumed to latch the cycle on the * write of the higher-numeric-address word, then ordered * writes work OK. * * - For reads, where a register contains a relevant value of more * that 32 bits, the hardware employs logic to latch the other * "half" of the data until read, ensuring an accurate value. * This is of particular relevance when dealing with CAAM's * performance counters. * */ extern bool caam_little_end; extern bool caam_imx; extern size_t caam_ptr_sz; #define caam_to_cpu(len) … #define cpu_to_caam(len) … caam_to_cpu(…) caam_to_cpu(…) caam_to_cpu(…) cpu_to_caam(…) cpu_to_caam(…) cpu_to_caam(…) static inline void wr_reg32(void __iomem *reg, u32 data) { … } static inline u32 rd_reg32(void __iomem *reg) { … } static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set) { … } /* * The only users of these wr/rd_reg64 functions is the Job Ring (JR). * The DMA address registers in the JR are handled differently depending on * platform: * * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): * * base + 0x0000 : most-significant 32 bits * base + 0x0004 : least-significant 32 bits * * The 32-bit version of this core therefore has to write to base + 0x0004 * to set the 32-bit wide DMA address. * * 2. All other LE CAAM platforms (LS1021A etc.) * base + 0x0000 : least-significant 32 bits * base + 0x0004 : most-significant 32 bits */ static inline void wr_reg64(void __iomem *reg, u64 data) { … } static inline u64 rd_reg64(void __iomem *reg) { … } static inline u64 cpu_to_caam_dma64(dma_addr_t value) { … } static inline u64 caam_dma64_to_cpu(u64 value) { … } static inline u64 cpu_to_caam_dma(u64 value) { … } static inline u64 caam_dma_to_cpu(u64 value) { … } /* * jr_outentry * Represents each entry in a JobR output ring */ static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc, u32 *jrstatus) { … } #define SIZEOF_JR_OUTENTRY … static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx) { … } static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx) { … } static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val) { … } #define SIZEOF_JR_INPENTRY … /* Version registers (Era 10+) e80-eff */ struct version_regs { … }; /* Version registers bitfields */ /* Number of CHAs instantiated */ #define CHA_VER_NUM_MASK … /* CHA Miscellaneous Information */ #define CHA_VER_MISC_SHIFT … #define CHA_VER_MISC_MASK … /* CHA Revision Number */ #define CHA_VER_REV_SHIFT … #define CHA_VER_REV_MASK … /* CHA Version ID */ #define CHA_VER_VID_SHIFT … #define CHA_VER_VID_MASK … /* CHA Miscellaneous Information - AESA_MISC specific */ #define CHA_VER_MISC_AES_NUM_MASK … #define CHA_VER_MISC_AES_GCM … /* CHA Miscellaneous Information - PKHA_MISC specific */ #define CHA_VER_MISC_PKHA_NO_CRYPT … /* * caam_perfmon - Performance Monitor/Secure Memory Status/ * CAAM Global Status/Component Version IDs * * Spans f00-fff wherever instantiated */ /* Number of DECOs */ #define CHA_NUM_MS_DECONUM_SHIFT … #define CHA_NUM_MS_DECONUM_MASK … /* * CHA version IDs / instantiation bitfields (< Era 10) * Defined for use with the cha_id fields in perfmon, but the same shift/mask * selectors can be used to pull out the number of instantiated blocks within * cha_num fields in perfmon because the locations are the same. */ #define CHA_ID_LS_AES_SHIFT … #define CHA_ID_LS_AES_MASK … #define CHA_ID_LS_DES_SHIFT … #define CHA_ID_LS_DES_MASK … #define CHA_ID_LS_ARC4_SHIFT … #define CHA_ID_LS_ARC4_MASK … #define CHA_ID_LS_MD_SHIFT … #define CHA_ID_LS_MD_MASK … #define CHA_ID_LS_RNG_SHIFT … #define CHA_ID_LS_RNG_MASK … #define CHA_ID_LS_SNW8_SHIFT … #define CHA_ID_LS_SNW8_MASK … #define CHA_ID_LS_KAS_SHIFT … #define CHA_ID_LS_KAS_MASK … #define CHA_ID_LS_PK_SHIFT … #define CHA_ID_LS_PK_MASK … #define CHA_ID_MS_CRC_SHIFT … #define CHA_ID_MS_CRC_MASK … #define CHA_ID_MS_SNW9_SHIFT … #define CHA_ID_MS_SNW9_MASK … #define CHA_ID_MS_DECO_SHIFT … #define CHA_ID_MS_DECO_MASK … #define CHA_ID_MS_JR_SHIFT … #define CHA_ID_MS_JR_MASK … /* Specific CHA version IDs */ #define CHA_VER_VID_AES_LP … #define CHA_VER_VID_AES_HP … #define CHA_VER_VID_MD_LP256 … #define CHA_VER_VID_MD_LP512 … #define CHA_VER_VID_MD_HP … struct sec_vid { … }; struct caam_perfmon { … }; /* LIODN programming for DMA configuration */ #define MSTRID_LOCK_LIODN … #define MSTRID_LOCK_MAKETRUSTED … #define MSTRID_LIODN_MASK … struct masterid { … }; /* RNGB test mode (replicated twice in some configurations) */ /* Padded out to 0x100 */ struct rngtst { … }; /* RNG4 TRNG test registers */ struct rng4tst { … }; /* * caam_ctrl - basic core configuration * starts base + 0x0000 padded out to 0x1000 */ #define KEK_KEY_SIZE … #define TKEK_KEY_SIZE … #define TDSK_KEY_SIZE … #define DECO_RESET … #define DECO_RESET_0 … #define DECO_RESET_1 … #define DECO_RESET_2 … #define DECO_RESET_3 … #define DECO_RESET_4 … struct caam_ctrl { … }; /* * Controller master config register defs */ #define MCFGR_SWRESET … #define MCFGR_WDENABLE … #define MCFGR_WDFAIL … #define MCFGR_DMA_RESET … #define MCFGR_LONG_PTR … #define SCFGR_RDBENABLE … #define SCFGR_VIRT_EN … #define DECORR_RQD0ENABLE … #define DECORSR_JR0 … #define DECORSR_VALID … #define DECORR_DEN0 … /* AXI read cache control */ #define MCFGR_ARCACHE_SHIFT … #define MCFGR_ARCACHE_MASK … #define MCFGR_ARCACHE_BUFF … #define MCFGR_ARCACHE_CACH … #define MCFGR_ARCACHE_RALL … /* AXI write cache control */ #define MCFGR_AWCACHE_SHIFT … #define MCFGR_AWCACHE_MASK … #define MCFGR_AWCACHE_BUFF … #define MCFGR_AWCACHE_CACH … #define MCFGR_AWCACHE_WALL … /* AXI pipeline depth */ #define MCFGR_AXIPIPE_SHIFT … #define MCFGR_AXIPIPE_MASK … #define MCFGR_AXIPRI … #define MCFGR_LARGE_BURST … #define MCFGR_BURST_64 … /* JRSTART register offsets */ #define JRSTART_JR0_START … #define JRSTART_JR1_START … #define JRSTART_JR2_START … #define JRSTART_JR3_START … /* * caam_job_ring - direct job ring setup * 1-4 possible per instantiation, base + 1000/2000/3000/4000 * Padded out to 0x1000 */ struct caam_job_ring { … }; #define JR_RINGSIZE_MASK … /* * jrstatus - Job Ring Output Status * All values in lo word * Also note, same values written out as status through QI * in the command/status field of a frame descriptor */ #define JRSTA_SSRC_SHIFT … #define JRSTA_SSRC_MASK … #define JRSTA_SSRC_NONE … #define JRSTA_SSRC_CCB_ERROR … #define JRSTA_SSRC_JUMP_HALT_USER … #define JRSTA_SSRC_DECO … #define JRSTA_SSRC_QI … #define JRSTA_SSRC_JRERROR … #define JRSTA_SSRC_JUMP_HALT_CC … #define JRSTA_DECOERR_JUMP … #define JRSTA_DECOERR_INDEX_SHIFT … #define JRSTA_DECOERR_INDEX_MASK … #define JRSTA_DECOERR_ERROR_MASK … #define JRSTA_DECOERR_NONE … #define JRSTA_DECOERR_LINKLEN … #define JRSTA_DECOERR_LINKPTR … #define JRSTA_DECOERR_JRCTRL … #define JRSTA_DECOERR_DESCCMD … #define JRSTA_DECOERR_ORDER … #define JRSTA_DECOERR_KEYCMD … #define JRSTA_DECOERR_LOADCMD … #define JRSTA_DECOERR_STORECMD … #define JRSTA_DECOERR_OPCMD … #define JRSTA_DECOERR_FIFOLDCMD … #define JRSTA_DECOERR_FIFOSTCMD … #define JRSTA_DECOERR_MOVECMD … #define JRSTA_DECOERR_JUMPCMD … #define JRSTA_DECOERR_MATHCMD … #define JRSTA_DECOERR_SHASHCMD … #define JRSTA_DECOERR_SEQCMD … #define JRSTA_DECOERR_DECOINTERNAL … #define JRSTA_DECOERR_SHDESCHDR … #define JRSTA_DECOERR_HDRLEN … #define JRSTA_DECOERR_BURSTER … #define JRSTA_DECOERR_DESCSIGNATURE … #define JRSTA_DECOERR_DMA … #define JRSTA_DECOERR_BURSTFIFO … #define JRSTA_DECOERR_JRRESET … #define JRSTA_DECOERR_JOBFAIL … #define JRSTA_DECOERR_DNRERR … #define JRSTA_DECOERR_UNDEFPCL … #define JRSTA_DECOERR_PDBERR … #define JRSTA_DECOERR_ANRPLY_LATE … #define JRSTA_DECOERR_ANRPLY_REPLAY … #define JRSTA_DECOERR_SEQOVF … #define JRSTA_DECOERR_INVSIGN … #define JRSTA_DECOERR_DSASIGN … #define JRSTA_QIERR_ERROR_MASK … #define JRSTA_CCBERR_JUMP … #define JRSTA_CCBERR_INDEX_MASK … #define JRSTA_CCBERR_INDEX_SHIFT … #define JRSTA_CCBERR_CHAID_MASK … #define JRSTA_CCBERR_CHAID_SHIFT … #define JRSTA_CCBERR_ERRID_MASK … #define JRSTA_CCBERR_CHAID_AES … #define JRSTA_CCBERR_CHAID_DES … #define JRSTA_CCBERR_CHAID_ARC4 … #define JRSTA_CCBERR_CHAID_MD … #define JRSTA_CCBERR_CHAID_RNG … #define JRSTA_CCBERR_CHAID_SNOW … #define JRSTA_CCBERR_CHAID_KASUMI … #define JRSTA_CCBERR_CHAID_PK … #define JRSTA_CCBERR_CHAID_CRC … #define JRSTA_CCBERR_ERRID_NONE … #define JRSTA_CCBERR_ERRID_MODE … #define JRSTA_CCBERR_ERRID_DATASIZ … #define JRSTA_CCBERR_ERRID_KEYSIZ … #define JRSTA_CCBERR_ERRID_PKAMEMSZ … #define JRSTA_CCBERR_ERRID_PKBMEMSZ … #define JRSTA_CCBERR_ERRID_SEQUENCE … #define JRSTA_CCBERR_ERRID_PKDIVZRO … #define JRSTA_CCBERR_ERRID_PKMODEVN … #define JRSTA_CCBERR_ERRID_KEYPARIT … #define JRSTA_CCBERR_ERRID_ICVCHK … #define JRSTA_CCBERR_ERRID_HARDWARE … #define JRSTA_CCBERR_ERRID_CCMAAD … #define JRSTA_CCBERR_ERRID_INVCHA … #define JRINT_ERR_INDEX_MASK … #define JRINT_ERR_INDEX_SHIFT … #define JRINT_ERR_TYPE_MASK … #define JRINT_ERR_TYPE_SHIFT … #define JRINT_ERR_HALT_MASK … #define JRINT_ERR_HALT_SHIFT … #define JRINT_ERR_HALT_INPROGRESS … #define JRINT_ERR_HALT_COMPLETE … #define JRINT_JR_ERROR … #define JRINT_JR_INT … #define JRINT_ERR_TYPE_WRITE … #define JRINT_ERR_TYPE_BAD_INPADDR … #define JRINT_ERR_TYPE_BAD_OUTADDR … #define JRINT_ERR_TYPE_INV_INPWRT … #define JRINT_ERR_TYPE_INV_OUTWRT … #define JRINT_ERR_TYPE_RESET … #define JRINT_ERR_TYPE_REMOVE_OFL … #define JRINT_ERR_TYPE_ADD_OFL … #define JRCFG_SOE … #define JRCFG_ICEN … #define JRCFG_IMSK … #define JRCFG_ICDCT_SHIFT … #define JRCFG_ICTT_SHIFT … #define JRCR_RESET … /* * caam_assurance - Assurance Controller View * base + 0x6000 padded out to 0x1000 */ struct rtic_element { … }; struct rtic_block { … }; struct rtic_memhash { … }; struct caam_assurance { … }; /* * caam_queue_if - QI configuration and control * starts base + 0x7000, padded out to 0x1000 long */ struct caam_queue_if { … }; /* QI control bits - low word */ #define QICTL_DQEN … #define QICTL_STOP … #define QICTL_SOE … /* QI control bits - high word */ #define QICTL_MBSI … #define QICTL_MHWSI … #define QICTL_MWSI … #define QICTL_MDWSI … #define QICTL_CBSI … #define QICTL_CHWSI … #define QICTL_CWSI … #define QICTL_CDWSI … #define QICTL_MBSO … #define QICTL_MHWSO … #define QICTL_MWSO … #define QICTL_MDWSO … #define QICTL_CBSO … #define QICTL_CHWSO … #define QICTL_CWSO … #define QICTL_CDWSO … #define QICTL_DMBS … #define QICTL_EPO … /* QI status bits */ #define QISTA_PHRDERR … #define QISTA_CFRDERR … #define QISTA_OFWRERR … #define QISTA_BPDERR … #define QISTA_BTSERR … #define QISTA_CFWRERR … #define QISTA_STOPD … /* deco_sg_table - DECO view of scatter/gather table */ struct deco_sg_table { … }; /* * caam_deco - descriptor controller - CHA cluster block * * Only accessible when direct DECO access is turned on * (done in DECORR, via MID programmed in DECOxMID * * 5 typical, base + 0x8000/9000/a000/b000 * Padded out to 0x1000 long */ struct caam_deco { … }; #define DECO_STAT_HOST_ERR … #define DECO_JQCR_WHL … #define DECO_JQCR_FOUR … #define JR_BLOCK_NUMBER … #define ASSURE_BLOCK_NUMBER … #define QI_BLOCK_NUMBER … #define DECO_BLOCK_NUMBER … #define PG_SIZE_4K … #define PG_SIZE_64K … #endif /* REGS_H */
Codebase Browser
linux