/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ /* * Copyright (c) 2022 Collabora Ltd. * Author: AngeloGioacchino Del Regno <[email protected]> */ #ifndef _DT_BINDINGS_CLK_MT6795_H #define _DT_BINDINGS_CLK_MT6795_H /* TOPCKGEN */ #define CLK_TOP_ADSYS_26M … #define CLK_TOP_CLKPH_MCK_O … #define CLK_TOP_USB_SYSPLL_125M … #define CLK_TOP_DSI0_DIG … #define CLK_TOP_DSI1_DIG … #define CLK_TOP_ARMCA53PLL_754M … #define CLK_TOP_ARMCA53PLL_502M … #define CLK_TOP_MAIN_H546M … #define CLK_TOP_MAIN_H364M … #define CLK_TOP_MAIN_H218P4M … #define CLK_TOP_MAIN_H156M … #define CLK_TOP_TVDPLL_445P5M … #define CLK_TOP_TVDPLL_594M … #define CLK_TOP_UNIV_624M … #define CLK_TOP_UNIV_416M … #define CLK_TOP_UNIV_249P6M … #define CLK_TOP_UNIV_178P3M … #define CLK_TOP_UNIV_48M … #define CLK_TOP_CLKRTC_EXT … #define CLK_TOP_CLKRTC_INT … #define CLK_TOP_FPC … #define CLK_TOP_HDMITXPLL_D2 … #define CLK_TOP_HDMITXPLL_D3 … #define CLK_TOP_ARMCA53PLL_D2 … #define CLK_TOP_ARMCA53PLL_D3 … #define CLK_TOP_APLL1 … #define CLK_TOP_APLL2 … #define CLK_TOP_DMPLL … #define CLK_TOP_DMPLL_D2 … #define CLK_TOP_DMPLL_D4 … #define CLK_TOP_DMPLL_D8 … #define CLK_TOP_DMPLL_D16 … #define CLK_TOP_MMPLL … #define CLK_TOP_MMPLL_D2 … #define CLK_TOP_MSDCPLL … #define CLK_TOP_MSDCPLL_D2 … #define CLK_TOP_MSDCPLL_D4 … #define CLK_TOP_MSDCPLL2 … #define CLK_TOP_MSDCPLL2_D2 … #define CLK_TOP_MSDCPLL2_D4 … #define CLK_TOP_SYSPLL_D2 … #define CLK_TOP_SYSPLL1_D2 … #define CLK_TOP_SYSPLL1_D4 … #define CLK_TOP_SYSPLL1_D8 … #define CLK_TOP_SYSPLL1_D16 … #define CLK_TOP_SYSPLL_D3 … #define CLK_TOP_SYSPLL2_D2 … #define CLK_TOP_SYSPLL2_D4 … #define CLK_TOP_SYSPLL_D5 … #define CLK_TOP_SYSPLL3_D2 … #define CLK_TOP_SYSPLL3_D4 … #define CLK_TOP_SYSPLL_D7 … #define CLK_TOP_SYSPLL4_D2 … #define CLK_TOP_SYSPLL4_D4 … #define CLK_TOP_TVDPLL … #define CLK_TOP_TVDPLL_D2 … #define CLK_TOP_TVDPLL_D4 … #define CLK_TOP_TVDPLL_D8 … #define CLK_TOP_TVDPLL_D16 … #define CLK_TOP_UNIVPLL_D2 … #define CLK_TOP_UNIVPLL1_D2 … #define CLK_TOP_UNIVPLL1_D4 … #define CLK_TOP_UNIVPLL1_D8 … #define CLK_TOP_UNIVPLL_D3 … #define CLK_TOP_UNIVPLL2_D2 … #define CLK_TOP_UNIVPLL2_D4 … #define CLK_TOP_UNIVPLL2_D8 … #define CLK_TOP_UNIVPLL_D5 … #define CLK_TOP_UNIVPLL3_D2 … #define CLK_TOP_UNIVPLL3_D4 … #define CLK_TOP_UNIVPLL3_D8 … #define CLK_TOP_UNIVPLL_D7 … #define CLK_TOP_UNIVPLL_D26 … #define CLK_TOP_UNIVPLL_D52 … #define CLK_TOP_VCODECPLL … #define CLK_TOP_VCODECPLL_370P5 … #define CLK_TOP_VENCPLL … #define CLK_TOP_VENCPLL_D2 … #define CLK_TOP_VENCPLL_D4 … #define CLK_TOP_AXI_SEL … #define CLK_TOP_MEM_SEL … #define CLK_TOP_DDRPHYCFG_SEL … #define CLK_TOP_MM_SEL … #define CLK_TOP_PWM_SEL … #define CLK_TOP_VDEC_SEL … #define CLK_TOP_VENC_SEL … #define CLK_TOP_MFG_SEL … #define CLK_TOP_CAMTG_SEL … #define CLK_TOP_UART_SEL … #define CLK_TOP_SPI_SEL … #define CLK_TOP_USB20_SEL … #define CLK_TOP_USB30_SEL … #define CLK_TOP_MSDC50_0_H_SEL … #define CLK_TOP_MSDC50_0_SEL … #define CLK_TOP_MSDC30_1_SEL … #define CLK_TOP_MSDC30_2_SEL … #define CLK_TOP_MSDC30_3_SEL … #define CLK_TOP_AUDIO_SEL … #define CLK_TOP_AUD_INTBUS_SEL … #define CLK_TOP_PMICSPI_SEL … #define CLK_TOP_SCP_SEL … #define CLK_TOP_MJC_SEL … #define CLK_TOP_DPI0_SEL … #define CLK_TOP_IRDA_SEL … #define CLK_TOP_CCI400_SEL … #define CLK_TOP_AUD_1_SEL … #define CLK_TOP_AUD_2_SEL … #define CLK_TOP_MEM_MFG_IN_SEL … #define CLK_TOP_AXI_MFG_IN_SEL … #define CLK_TOP_SCAM_SEL … #define CLK_TOP_I2S0_M_SEL … #define CLK_TOP_I2S1_M_SEL … #define CLK_TOP_I2S2_M_SEL … #define CLK_TOP_I2S3_M_SEL … #define CLK_TOP_I2S3_B_SEL … #define CLK_TOP_APLL1_DIV0 … #define CLK_TOP_APLL1_DIV1 … #define CLK_TOP_APLL1_DIV2 … #define CLK_TOP_APLL1_DIV3 … #define CLK_TOP_APLL1_DIV4 … #define CLK_TOP_APLL1_DIV5 … #define CLK_TOP_APLL2_DIV0 … #define CLK_TOP_APLL2_DIV1 … #define CLK_TOP_APLL2_DIV2 … #define CLK_TOP_APLL2_DIV3 … #define CLK_TOP_APLL2_DIV4 … #define CLK_TOP_APLL2_DIV5 … #define CLK_TOP_NR_CLK … /* APMIXED_SYS */ #define CLK_APMIXED_ARMCA53PLL … #define CLK_APMIXED_MAINPLL … #define CLK_APMIXED_UNIVPLL … #define CLK_APMIXED_MMPLL … #define CLK_APMIXED_MSDCPLL … #define CLK_APMIXED_VENCPLL … #define CLK_APMIXED_TVDPLL … #define CLK_APMIXED_MPLL … #define CLK_APMIXED_VCODECPLL … #define CLK_APMIXED_APLL1 … #define CLK_APMIXED_APLL2 … #define CLK_APMIXED_REF2USB_TX … #define CLK_APMIXED_NR_CLK … /* INFRA_SYS */ #define CLK_INFRA_DBGCLK … #define CLK_INFRA_SMI … #define CLK_INFRA_AUDIO … #define CLK_INFRA_GCE … #define CLK_INFRA_L2C_SRAM … #define CLK_INFRA_M4U … #define CLK_INFRA_MD1MCU … #define CLK_INFRA_MD1BUS … #define CLK_INFRA_MD1DBB … #define CLK_INFRA_DEVICE_APC … #define CLK_INFRA_TRNG … #define CLK_INFRA_MD1LTE … #define CLK_INFRA_CPUM … #define CLK_INFRA_KP … #define CLK_INFRA_CA53_C0_SEL … #define CLK_INFRA_CA53_C1_SEL … #define CLK_INFRA_NR_CLK … /* PERI_SYS */ #define CLK_PERI_NFI … #define CLK_PERI_THERM … #define CLK_PERI_PWM1 … #define CLK_PERI_PWM2 … #define CLK_PERI_PWM3 … #define CLK_PERI_PWM4 … #define CLK_PERI_PWM5 … #define CLK_PERI_PWM6 … #define CLK_PERI_PWM7 … #define CLK_PERI_PWM … #define CLK_PERI_USB0 … #define CLK_PERI_USB1 … #define CLK_PERI_AP_DMA … #define CLK_PERI_MSDC30_0 … #define CLK_PERI_MSDC30_1 … #define CLK_PERI_MSDC30_2 … #define CLK_PERI_MSDC30_3 … #define CLK_PERI_NLI_ARB … #define CLK_PERI_IRDA … #define CLK_PERI_UART0 … #define CLK_PERI_UART1 … #define CLK_PERI_UART2 … #define CLK_PERI_UART3 … #define CLK_PERI_I2C0 … #define CLK_PERI_I2C1 … #define CLK_PERI_I2C2 … #define CLK_PERI_I2C3 … #define CLK_PERI_I2C4 … #define CLK_PERI_AUXADC … #define CLK_PERI_SPI0 … #define CLK_PERI_UART0_SEL … #define CLK_PERI_UART1_SEL … #define CLK_PERI_UART2_SEL … #define CLK_PERI_UART3_SEL … #define CLK_PERI_NR_CLK … /* MFG */ #define CLK_MFG_BAXI … #define CLK_MFG_BMEM … #define CLK_MFG_BG3D … #define CLK_MFG_B26M … #define CLK_MFG_NR_CLK … /* MM_SYS */ #define CLK_MM_SMI_COMMON … #define CLK_MM_SMI_LARB0 … #define CLK_MM_CAM_MDP … #define CLK_MM_MDP_RDMA0 … #define CLK_MM_MDP_RDMA1 … #define CLK_MM_MDP_RSZ0 … #define CLK_MM_MDP_RSZ1 … #define CLK_MM_MDP_RSZ2 … #define CLK_MM_MDP_TDSHP0 … #define CLK_MM_MDP_TDSHP1 … #define CLK_MM_MDP_CROP … #define CLK_MM_MDP_WDMA … #define CLK_MM_MDP_WROT0 … #define CLK_MM_MDP_WROT1 … #define CLK_MM_FAKE_ENG … #define CLK_MM_MUTEX_32K … #define CLK_MM_DISP_OVL0 … #define CLK_MM_DISP_OVL1 … #define CLK_MM_DISP_RDMA0 … #define CLK_MM_DISP_RDMA1 … #define CLK_MM_DISP_RDMA2 … #define CLK_MM_DISP_WDMA0 … #define CLK_MM_DISP_WDMA1 … #define CLK_MM_DISP_COLOR0 … #define CLK_MM_DISP_COLOR1 … #define CLK_MM_DISP_AAL … #define CLK_MM_DISP_GAMMA … #define CLK_MM_DISP_UFOE … #define CLK_MM_DISP_SPLIT0 … #define CLK_MM_DISP_SPLIT1 … #define CLK_MM_DISP_MERGE … #define CLK_MM_DISP_OD … #define CLK_MM_DISP_PWM0MM … #define CLK_MM_DISP_PWM026M … #define CLK_MM_DISP_PWM1MM … #define CLK_MM_DISP_PWM126M … #define CLK_MM_DSI0_ENGINE … #define CLK_MM_DSI0_DIGITAL … #define CLK_MM_DSI1_ENGINE … #define CLK_MM_DSI1_DIGITAL … #define CLK_MM_DPI_PIXEL … #define CLK_MM_DPI_ENGINE … #define CLK_MM_NR_CLK … /* VDEC_SYS */ #define CLK_VDEC_CKEN … #define CLK_VDEC_LARB_CKEN … #define CLK_VDEC_NR_CLK … /* VENC_SYS */ #define CLK_VENC_LARB … #define CLK_VENC_VENC … #define CLK_VENC_JPGENC … #define CLK_VENC_JPGDEC … #define CLK_VENC_NR_CLK … #endif /* _DT_BINDINGS_CLK_MT6795_H */
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