linux/include/dt-bindings/reset/mediatek,mt6795-resets.h

/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
/*
 * Copyright (c) 2022 Collabora Ltd.
 * Author: AngeloGioacchino Del Regno <[email protected]>
 */

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795
#define _DT_BINDINGS_RESET_CONTROLLER_MT6795

/* INFRACFG resets */
#define MT6795_INFRA_RST0_SCPSYS_RST …
#define MT6795_INFRA_RST0_PMIC_WRAP_RST …
#define MT6795_INFRA_RST1_MIPI_DSI_RST …
#define MT6795_INFRA_RST1_MIPI_CSI_RST …
#define MT6795_INFRA_RST1_MM_IOMMU_RST …

/* MMSYS resets */
#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON …
#define MT6795_MMSYS_SW0_RST_B_SMI_LARB …
#define MT6795_MMSYS_SW0_RST_B_CAM_MDP …
#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 …
#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 …
#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 …
#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 …
#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 …
#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 …
#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 …
#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA …
#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 …
#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 …
#define MT6795_MMSYS_SW0_RST_B_MDP_CROP …

/*  PERICFG resets */
#define MT6795_PERI_NFI_SW_RST …
#define MT6795_PERI_THERM_SW_RST …
#define MT6795_PERI_MSDC1_SW_RST …

/* TOPRGU resets */
#define MT6795_TOPRGU_INFRA_SW_RST …
#define MT6795_TOPRGU_MM_SW_RST …
#define MT6795_TOPRGU_MFG_SW_RST …
#define MT6795_TOPRGU_VENC_SW_RST …
#define MT6795_TOPRGU_VDEC_SW_RST …
#define MT6795_TOPRGU_IMG_SW_RST …
#define MT6795_TOPRGU_DDRPHY_SW_RST …
#define MT6795_TOPRGU_MD_SW_RST …
#define MT6795_TOPRGU_INFRA_AO_SW_RST …
#define MT6795_TOPRGU_MD_LITE_SW_RST …
#define MT6795_TOPRGU_APMIXED_SW_RST …
#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST …
#define MT6795_TOPRGU_SW_RST_NUM …

#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */